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Fri, 1 Sep 2023 03:41:03 -0500 From: Srinivas Goud To: , , , , , , , , , CC: , , , , , , , , , "Srinivas Goud" Subject: [PATCH v4 1/3] dt-bindings: can: xilinx_can: Add ECC property 'xlnx,has-ecc' Date: Fri, 1 Sep 2023 14:10:43 +0530 Message-ID: <1693557645-2728466-2-git-send-email-srinivas.goud@amd.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1693557645-2728466-1-git-send-email-srinivas.goud@amd.com> References: <1693557645-2728466-1-git-send-email-srinivas.goud@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A102:EE_|DS0PR12MB7769:EE_ X-MS-Office365-Filtering-Correlation-Id: 5a60b809-52c0-47fb-6e1b-08dbaac73062 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: z/SRXZwxN4qn337hC3o9Q6OjnWzIribHHxIUDni8Q7cakiKYaY8kN1ozbmUIBgac3MD32RxYRBHo9jCB9Q0XGBzJARCJ8uB2yX2Gggxx4zZz5JcGMWoG0OkiQSbJo7L8QE/JOUPNVtVEJ5mw/jx2Yy/37T0wojSCi0DeociOLDrcjCVr2OEKhkU8dRIsIPM6x9api96NTGciqqCaO+foVKUuReSj3Kr3Ez5Og4pMjzWXh/ldDijwAv5yfzXUjCXOJTLgFLDl9Tv1vFQFYh1qnlxj3t7am7fdw60F4+DQsYIlLVsEr9EEhPk2bagLh64JpMRZKoZOSgzscSYVheRZ+EmpDv9britJJTHBvLkTYkLW74kodypkRcsZZv1N1UJjkeGu48Je/DW9fmYCmEL8UDvCE7xCu/DrJeXRliI88gY4FPfL5P016wLebC7G21BN+gcw711n4C1lDEtVallz1Z+dqOIwM+10JrGlf0Ak/AIcqEKj44Z7xOGa7eWg7ia5/31o7TA4jja0tPi8dCdMteFVBlFDb09NhFNiRw8Oaxh1NHve/qWKQgLUA1ClJNSzSyL/Jm2LVY0DIg3xxWg4twh3RK4fP47GQ0ZY1fuo/q92g9WVKXL0SmRMCx4Bd2nCD0pPmwGoJTy+VDosDF1XB6uMMrbeVgZmemkRjMgmwEJtSqIMSOFc2PRKHLhQvCErzzEY8QRuQWw6L9afn2zY4aqdLgHrfsGC5QYF5qopcEJ06RMeLmh/kMkhv5/hk5SHvccRszfgsBrtOTauzyoNS65XRJX68RaNW8YyiNBa+n8= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(136003)(346002)(396003)(376002)(39860400002)(186009)(82310400011)(1800799009)(451199024)(46966006)(36840700001)(40470700004)(478600001)(40460700003)(41300700001)(336012)(26005)(356005)(921005)(82740400003)(81166007)(86362001)(83380400001)(6666004)(47076005)(7416002)(36860700001)(40480700001)(2616005)(426003)(70206006)(316002)(110136005)(54906003)(36756003)(2906002)(5660300002)(4326008)(8676002)(8936002)(44832011)(70586007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Sep 2023 08:41:08.9715 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5a60b809-52c0-47fb-6e1b-08dbaac73062 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A102.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7769 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" ECC feature added to Tx and Rx FIFOs for Xilinx AXI CAN Controller. Part of this feature configuration and counter registers added in IP for 1bit/2bit ECC errors. xlnx,has-ecc is optional property and added to Xilinx AXI CAN Controller node if ECC block enabled in the HW Signed-off-by: Srinivas Goud --- Changes in v4: Fix binding check warning Update property description=20 Changes in v3: Update commit description Changes in v2: None Documentation/devicetree/bindings/net/can/xilinx,can.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml b/Do= cumentation/devicetree/bindings/net/can/xilinx,can.yaml index 64d57c3..50a2671 100644 --- a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml +++ b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml @@ -49,6 +49,10 @@ properties: resets: maxItems: 1 =20 + xlnx,has-ecc: + $ref: /schemas/types.yaml#/definitions/flag + description: CAN Tx and Rx fifo has ECC (AXI CAN) + required: - compatible - reg @@ -137,6 +141,7 @@ examples: interrupts =3D ; tx-fifo-depth =3D <0x40>; rx-fifo-depth =3D <0x40>; + xlnx,has-ecc; }; =20 - | --=20 2.1.1 From nobody Sun Feb 8 18:30:13 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7DF83CA0FE8 for ; Fri, 1 Sep 2023 08:41:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345690AbjIAIlY (ORCPT ); Fri, 1 Sep 2023 04:41:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33266 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344165AbjIAIlW (ORCPT ); Fri, 1 Sep 2023 04:41:22 -0400 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2072.outbound.protection.outlook.com [40.107.243.72]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 05C1E10E9; Fri, 1 Sep 2023 01:41:18 -0700 (PDT) ARC-Seal: i=1; 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Fri, 1 Sep 2023 03:41:08 -0500 From: Srinivas Goud To: , , , , , , , , , CC: , , , , , , , , , "Srinivas Goud" Subject: [PATCH v4 2/3] can: xilinx_can: Add ECC support Date: Fri, 1 Sep 2023 14:10:44 +0530 Message-ID: <1693557645-2728466-3-git-send-email-srinivas.goud@amd.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1693557645-2728466-1-git-send-email-srinivas.goud@amd.com> References: <1693557645-2728466-1-git-send-email-srinivas.goud@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECD7:EE_|DM4PR12MB7623:EE_ X-MS-Office365-Filtering-Correlation-Id: eb074498-e5b8-4ddc-13e1-08dbaac73428 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: RMw6r26D/0yXibKgbB3B+rFvwIXoFR+lG2HM5CUru6pNoj80n7lvc6qio5gwFukQbWeRrVKk9fG7jmHvuhr6kEFNSIpEvZoB+78e1z7x9v9Y3xCUwqffKv756aeymKf3nNujNlbBWTXO3F9/XLFgXDbOnPOOx0BcPIdRfc9nYS8oH6pxlpkm45h0r0hffAw4NWWh6n/aDRrlYmNCIUF2oUIlTyv1uXMf6WI5JILCk3pw7QBQGRvVqnzS57Ju5uLUWJGumO0N70oBAcOPtVXls1GfkQnxv/1igr13JLGxe6h5tAPla/tOl78dVZqvxCKlqfmk9neL7IRw2VmnOBMyeyXMFEPhQnZzI/VS71gilxxCfS3HP8N4JzE8T6PHaiX0Y3sKR8vmd/SDhznmyp4G469bjMCRL5G9uky8MXVxYyIOLTHriRPQoq4yzXsALF8lxKG619uF2jQyzpNN0Wr5dgLUEZsv8pKcHTlvZs3/mIsoO/ELseDxAY7aqxrgh8KtT0XCDy9h5OeId3zpD+jhE+QIQ01UXPHOa7rcb1bxlHCXiqDE2SnPX/rQHE7h/+toIl+gXqNV9H6ZcGEjdLVKFC9WBGq2nI2vAYGLaPVeLHc8RtcoDr5YkkIQJek8pkw+1GOz6YEDA+cM1JfNAfM4W8Owg0+aCLdQneQhCQHPp35f2yp9+oPGYqZRkDYXzGGY+O7xG6/RFjOkadJEAPXRlMUzETNG0xfoGQb16IQ1aiZntHMOZUEeNStJnF7FYt3BUlc3N9lfwKI4pzgPMrsrkiS/95QK9ZurjmcmH4fb0JE= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(376002)(346002)(136003)(396003)(39860400002)(186009)(451199024)(1800799009)(82310400011)(40470700004)(46966006)(36840700001)(40480700001)(40460700003)(7416002)(316002)(70586007)(70206006)(54906003)(921005)(356005)(110136005)(82740400003)(81166007)(478600001)(2906002)(41300700001)(44832011)(86362001)(8936002)(8676002)(5660300002)(4326008)(83380400001)(47076005)(36860700001)(336012)(2616005)(6666004)(26005)(426003)(36756003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Sep 2023 08:41:15.3000 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eb074498-e5b8-4ddc-13e1-08dbaac73428 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD7.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7623 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add ECC support for Xilinx CAN Controller, so this driver reports 1bit/2bit ECC errors for FIFO's based on ECC error interrupt. ECC feature for Xilinx CAN Controller selected through 'xlnx,has-ecc' DT property Signed-off-by: Srinivas Goud --- Changes in v4: None Changes in v3: None Changes in v2: Address review comments drivers/net/can/xilinx_can.c | 129 ++++++++++++++++++++++++++++++++++++++-= ---- 1 file changed, 114 insertions(+), 15 deletions(-) diff --git a/drivers/net/can/xilinx_can.c b/drivers/net/can/xilinx_can.c index abe58f1..798b32b 100644 --- a/drivers/net/can/xilinx_can.c +++ b/drivers/net/can/xilinx_can.c @@ -53,18 +53,23 @@ enum xcan_reg { XCAN_AFR_OFFSET =3D 0x60, /* Acceptance Filter */ =20 /* only on CAN FD cores */ - XCAN_F_BRPR_OFFSET =3D 0x088, /* Data Phase Baud Rate - * Prescaler - */ - XCAN_F_BTR_OFFSET =3D 0x08C, /* Data Phase Bit Timing */ - XCAN_TRR_OFFSET =3D 0x0090, /* TX Buffer Ready Request */ - XCAN_AFR_EXT_OFFSET =3D 0x00E0, /* Acceptance Filter */ - XCAN_FSR_OFFSET =3D 0x00E8, /* RX FIFO Status */ - XCAN_TXMSG_BASE_OFFSET =3D 0x0100, /* TX Message Space */ + XCAN_F_BRPR_OFFSET =3D 0x88, /* Data Phase Baud Rate Prescaler */ + XCAN_F_BTR_OFFSET =3D 0x8C, /* Data Phase Bit Timing */ + XCAN_TRR_OFFSET =3D 0x90, /* TX Buffer Ready Request */ + + /* only on AXI CAN cores */ + XCAN_ECC_CFG_OFFSET =3D 0xC8, /* ECC Configuration */ + XCAN_TXTLFIFO_ECC_OFFSET =3D 0xCC, /* TXTL FIFO ECC error counter = */ + XCAN_TXOLFIFO_ECC_OFFSET =3D 0xD0, /* TXOL FIFO ECC error counter = */ + XCAN_RXFIFO_ECC_OFFSET =3D 0xD4, /* RX FIFO ECC error counter */ + + XCAN_AFR_EXT_OFFSET =3D 0xE0, /* Acceptance Filter */ + XCAN_FSR_OFFSET =3D 0xE8, /* RX FIFO Status */ + XCAN_TXMSG_BASE_OFFSET =3D 0x100, /* TX Message Space */ + XCAN_AFR_2_MASK_OFFSET =3D 0xA00, /* Acceptance Filter MASK */ + XCAN_AFR_2_ID_OFFSET =3D 0xA04, /* Acceptance Filter ID */ XCAN_RXMSG_BASE_OFFSET =3D 0x1100, /* RX Message Space */ XCAN_RXMSG_2_BASE_OFFSET =3D 0x2100, /* RX Message Space */ - XCAN_AFR_2_MASK_OFFSET =3D 0x0A00, /* Acceptance Filter MASK */ - XCAN_AFR_2_ID_OFFSET =3D 0x0A04, /* Acceptance Filter ID */ }; =20 #define XCAN_FRAME_ID_OFFSET(frame_base) ((frame_base) + 0x00) @@ -124,6 +129,12 @@ enum xcan_reg { #define XCAN_IXR_TXFLL_MASK 0x00000004 /* Tx FIFO Full intr */ #define XCAN_IXR_TXOK_MASK 0x00000002 /* TX successful intr */ #define XCAN_IXR_ARBLST_MASK 0x00000001 /* Arbitration lost intr */ +#define XCAN_IXR_E2BERX_MASK BIT(23) /* RX FIFO two bit ECC err= or */ +#define XCAN_IXR_E1BERX_MASK BIT(22) /* RX FIFO one bit ECC err= or */ +#define XCAN_IXR_E2BETXOL_MASK BIT(21) /* TXOL FIFO two bit ECC e= rror */ +#define XCAN_IXR_E1BETXOL_MASK BIT(20) /* TXOL FIFO One bit ECC e= rror */ +#define XCAN_IXR_E2BETXTL_MASK BIT(19) /* TXTL FIFO Two bit ECC e= rror */ +#define XCAN_IXR_E1BETXTL_MASK BIT(18) /* TXTL FIFO One bit ECC e= rror */ #define XCAN_IDR_ID1_MASK 0xFFE00000 /* Standard msg identifier */ #define XCAN_IDR_SRR_MASK 0x00100000 /* Substitute remote TXreq */ #define XCAN_IDR_IDE_MASK 0x00080000 /* Identifier extension */ @@ -137,6 +148,11 @@ enum xcan_reg { #define XCAN_2_FSR_RI_MASK 0x0000003F /* RX Read Index */ #define XCAN_DLCR_EDL_MASK 0x08000000 /* EDL Mask in DLC */ #define XCAN_DLCR_BRS_MASK 0x04000000 /* BRS Mask in DLC */ +#define XCAN_ECC_CFG_REECRX_MASK BIT(2) /* Reset RX FIFO ECC error counter= s */ +#define XCAN_ECC_CFG_REECTXOL_MASK BIT(1) /* Reset TXOL FIFO ECC error cou= nters */ +#define XCAN_ECC_CFG_REECTXTL_MASK BIT(0) /* Reset TXTL FIFO ECC error cou= nters */ +#define XCAN_ECC_1BIT_CNT_MASK GENMASK(15, 0) /* FIFO ECC 1bit count mask= */ +#define XCAN_ECC_2BIT_CNT_MASK GENMASK(31, 16) /* FIFO ECC 2bit count mas= k */ =20 /* CAN register bit shift - XCAN___SHIFT */ #define XCAN_BRPR_TDC_ENABLE BIT(16) /* Transmitter Delay Compensation (T= DC) Enable */ @@ -202,6 +218,13 @@ struct xcan_devtype_data { * @devtype: Device type specific constants * @transceiver: Optional pointer to associated CAN transceiver * @rstc: Pointer to reset control + * @ecc_enable: ECC enable flag + * @ecc_2bit_rxfifo_cnt: RXFIFO 2bit ECC count + * @ecc_1bit_rxfifo_cnt: RXFIFO 1bit ECC count + * @ecc_2bit_txolfifo_cnt: TXOLFIFO 2bit ECC count + * @ecc_1bit_txolfifo_cnt: TXOLFIFO 1bit ECC count + * @ecc_2bit_txtlfifo_cnt: TXTLFIFO 2bit ECC count + * @ecc_1bit_txtlfifo_cnt: TXTLFIFO 1bit ECC count */ struct xcan_priv { struct can_priv can; @@ -221,6 +244,13 @@ struct xcan_priv { struct xcan_devtype_data devtype; struct phy *transceiver; struct reset_control *rstc; + bool ecc_enable; + u64 ecc_2bit_rxfifo_cnt; + u64 ecc_1bit_rxfifo_cnt; + u64 ecc_2bit_txolfifo_cnt; + u64 ecc_1bit_txolfifo_cnt; + u64 ecc_2bit_txtlfifo_cnt; + u64 ecc_1bit_txtlfifo_cnt; }; =20 /* CAN Bittiming constants as per Xilinx CAN specs */ @@ -523,6 +553,11 @@ static int xcan_chip_start(struct net_device *ndev) XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK | XCAN_IXR_ARBLST_MASK | xcan_rx_int_mask(priv); =20 + if (priv->ecc_enable) + ier |=3D XCAN_IXR_E2BERX_MASK | XCAN_IXR_E1BERX_MASK | + XCAN_IXR_E2BETXOL_MASK | XCAN_IXR_E1BETXOL_MASK | + XCAN_IXR_E2BETXTL_MASK | XCAN_IXR_E1BETXTL_MASK; + if (priv->devtype.flags & XCAN_FLAG_RXMNF) ier |=3D XCAN_IXR_RXMNF_MASK; =20 @@ -1127,6 +1162,58 @@ static void xcan_err_interrupt(struct net_device *nd= ev, u32 isr) priv->can.can_stats.bus_error++; } =20 + if (priv->ecc_enable) { + u32 reg_ecc; + + reg_ecc =3D priv->read_reg(priv, XCAN_RXFIFO_ECC_OFFSET); + if (isr & XCAN_IXR_E2BERX_MASK) { + priv->ecc_2bit_rxfifo_cnt +=3D + FIELD_GET(XCAN_ECC_2BIT_CNT_MASK, reg_ecc); + netdev_dbg(ndev, "%s: RX FIFO 2bit ECC error count %lld\n", + __func__, priv->ecc_2bit_rxfifo_cnt); + } + if (isr & XCAN_IXR_E1BERX_MASK) { + priv->ecc_1bit_rxfifo_cnt +=3D + FIELD_GET(XCAN_ECC_1BIT_CNT_MASK, reg_ecc); + netdev_dbg(ndev, "%s: RX FIFO 1bit ECC error count %lld\n", + __func__, priv->ecc_1bit_rxfifo_cnt); + } + + reg_ecc =3D priv->read_reg(priv, XCAN_TXOLFIFO_ECC_OFFSET); + if (isr & XCAN_IXR_E2BETXOL_MASK) { + priv->ecc_2bit_txolfifo_cnt +=3D + FIELD_GET(XCAN_ECC_2BIT_CNT_MASK, reg_ecc); + netdev_dbg(ndev, "%s: TXOL FIFO 2bit ECC error count %lld\n", + __func__, priv->ecc_2bit_txolfifo_cnt); + } + if (isr & XCAN_IXR_E1BETXOL_MASK) { + priv->ecc_1bit_txolfifo_cnt +=3D + FIELD_GET(XCAN_ECC_1BIT_CNT_MASK, reg_ecc); + netdev_dbg(ndev, "%s: TXOL FIFO 1bit ECC error count %lld\n", + __func__, priv->ecc_1bit_txolfifo_cnt); + } + + reg_ecc =3D priv->read_reg(priv, XCAN_TXTLFIFO_ECC_OFFSET); + if (isr & XCAN_IXR_E2BETXTL_MASK) { + priv->ecc_2bit_txtlfifo_cnt +=3D + FIELD_GET(XCAN_ECC_2BIT_CNT_MASK, reg_ecc); + netdev_dbg(ndev, "%s: TXTL FIFO 2bit ECC error count %lld\n", + __func__, priv->ecc_2bit_txtlfifo_cnt); + } + if (isr & XCAN_IXR_E1BETXTL_MASK) { + priv->ecc_1bit_txtlfifo_cnt +=3D + FIELD_GET(XCAN_ECC_1BIT_CNT_MASK, reg_ecc); + netdev_dbg(ndev, "%s: TXTL FIFO 1bit ECC error count %lld\n", + __func__, priv->ecc_1bit_txtlfifo_cnt); + } + + /* The counter reaches its maximum at 0xffff and does not overflow. + * Accept the small race window between reading and resetting ECC counte= rs. + */ + priv->write_reg(priv, XCAN_ECC_CFG_OFFSET, XCAN_ECC_CFG_REECRX_MASK | + XCAN_ECC_CFG_REECTXOL_MASK | XCAN_ECC_CFG_REECTXTL_MASK); + } + if (cf.can_id) { struct can_frame *skb_cf; struct sk_buff *skb =3D alloc_can_err_skb(ndev, &skb_cf); @@ -1354,9 +1441,8 @@ static irqreturn_t xcan_interrupt(int irq, void *dev_= id) { struct net_device *ndev =3D (struct net_device *)dev_id; struct xcan_priv *priv =3D netdev_priv(ndev); - u32 isr, ier; - u32 isr_errors; u32 rx_int_mask =3D xcan_rx_int_mask(priv); + u32 isr, ier, isr_errors, mask; =20 /* Get the interrupt status from Xilinx CAN */ isr =3D priv->read_reg(priv, XCAN_ISR_OFFSET); @@ -1374,10 +1460,17 @@ static irqreturn_t xcan_interrupt(int irq, void *de= v_id) if (isr & XCAN_IXR_TXOK_MASK) xcan_tx_interrupt(ndev, isr); =20 + mask =3D XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK | + XCAN_IXR_BSOFF_MASK | XCAN_IXR_ARBLST_MASK | + XCAN_IXR_RXMNF_MASK; + + if (priv->ecc_enable) + mask |=3D XCAN_IXR_E2BERX_MASK | XCAN_IXR_E1BERX_MASK | + XCAN_IXR_E2BETXOL_MASK | XCAN_IXR_E1BETXOL_MASK | + XCAN_IXR_E2BETXTL_MASK | XCAN_IXR_E1BETXTL_MASK; + /* Check for the type of error interrupt and Processing it */ - isr_errors =3D isr & (XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK | - XCAN_IXR_BSOFF_MASK | XCAN_IXR_ARBLST_MASK | - XCAN_IXR_RXMNF_MASK); + isr_errors =3D isr & mask; if (isr_errors) { priv->write_reg(priv, XCAN_ICR_OFFSET, isr_errors); xcan_err_interrupt(ndev, isr); @@ -1796,6 +1889,7 @@ static int xcan_probe(struct platform_device *pdev) return -ENOMEM; =20 priv =3D netdev_priv(ndev); + priv->ecc_enable =3D of_property_read_bool(pdev->dev.of_node, "xlnx,has-e= cc"); priv->dev =3D &pdev->dev; priv->can.bittiming_const =3D devtype->bittiming_const; priv->can.do_set_mode =3D xcan_do_set_mode; @@ -1912,6 +2006,11 @@ static int xcan_probe(struct platform_device *pdev) priv->reg_base, ndev->irq, priv->can.clock.freq, hw_tx_max, priv->tx_max); =20 + if (priv->ecc_enable) { + /* Reset FIFO ECC counters */ + priv->write_reg(priv, XCAN_ECC_CFG_OFFSET, XCAN_ECC_CFG_REECRX_MASK | + XCAN_ECC_CFG_REECTXOL_MASK | XCAN_ECC_CFG_REECTXTL_MASK); + } return 0; =20 err_disableclks: --=20 2.1.1 From nobody Sun Feb 8 18:30:13 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9C21CA0FE6 for ; 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Fri, 1 Sep 2023 03:41:13 -0500 From: Srinivas Goud To: , , , , , , , , , CC: , , , , , , , , , "Srinivas Goud" Subject: [PATCH v4 3/3] can: xilinx_can: Add ethtool stats interface for ECC errors Date: Fri, 1 Sep 2023 14:10:45 +0530 Message-ID: <1693557645-2728466-4-git-send-email-srinivas.goud@amd.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1693557645-2728466-1-git-send-email-srinivas.goud@amd.com> References: <1693557645-2728466-1-git-send-email-srinivas.goud@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECDA:EE_|BL1PR12MB5064:EE_ X-MS-Office365-Filtering-Correlation-Id: 5d71bc4e-fa2f-43f1-8f95-08dbaac73808 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qJSfobMd8VePigfoiI5zFhH/JN2xv42mH/8VtHvrDecKWkVKolnvQHE+tg3hjfHCGFJba7bt4D8Lct95eXTeuFfxb/2+VGiniq82IDVl95yXUP85MCBQLPItFCdmBMPOPTXL/aO1BblfVwDvthbcVTdLh1ZnmfdFS0GmkKM6TJA3FKDG7ZM2uQSpDv7Ic2+n6tivH3YY2CrVl4101LtF12b2P0nbYNAp2djI6vSFccJ+OnzvjzkbwfHcLJHobxFPPoLemuV9Gsv5muayjn4z9ziPj8Tj6kUPanODWsY57IRHj3hMPBOI1CF5WW3zp3Q9bTf+as5tisAsxMMwNr0G3Ol2AAWK1GqF9QDFNvdlcFk5UGompkIjtZNcSYJ/J1ZpwFyJEqDx/sm0DJbi6aDJ86yCmczSOmK5WDyfL/W8HmeFGKAqWWSQuB7Sn2eNIx9accMEGHi1mun0XWrAEFs2vDYE92T6ZCN8Pz70jRhRZUTJC8nwuoXYMNuAjprZo8Jm62epJBrhElzO1e4fsk8AMu9EF+ofp14w9GWgY4nNoOhf3FFQ6jmTnwDv0ykUwuKdPfS7vwH5OQwPxP7E2s98u6wLrN8mOmhxVw7hysGr26AEyU1TzB/Jl5GSh9WZusSPbqG85njrs/PeBvwBzElfjtX5XDF+wuNJ8CbPbeqnOJ/vCBr9yViOJ8EtnLCIb+RQwXWb+v8SrNtVwO9eG7YVRPCN83/b1EdGPUnnI1uBREP1SCgmvArhr7ppO2MWh1lozvmcSQ4t5/YI6SES92I02+Fc56XQecZKGYyiMz+oF4M= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(376002)(396003)(346002)(136003)(186009)(82310400011)(1800799009)(451199024)(36840700001)(40470700004)(46966006)(6666004)(478600001)(83380400001)(2616005)(26005)(336012)(426003)(2906002)(7416002)(44832011)(54906003)(316002)(41300700001)(70206006)(70586007)(110136005)(5660300002)(8676002)(8936002)(4326008)(40460700003)(40480700001)(47076005)(36756003)(36860700001)(86362001)(82740400003)(81166007)(921005)(356005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Sep 2023 08:41:21.7887 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5d71bc4e-fa2f-43f1-8f95-08dbaac73808 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECDA.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5064 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add ethtool stats interface for reading FIFO 1bit/2bit ECC errors information. Signed-off-by: Srinivas Goud --- Changes in v4: None Changes in v3: None Changes in v2: Add ethtool stats interface drivers/net/can/xilinx_can.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/net/can/xilinx_can.c b/drivers/net/can/xilinx_can.c index 798b32b..50e0c9d 100644 --- a/drivers/net/can/xilinx_can.c +++ b/drivers/net/can/xilinx_can.c @@ -219,6 +219,7 @@ struct xcan_devtype_data { * @transceiver: Optional pointer to associated CAN transceiver * @rstc: Pointer to reset control * @ecc_enable: ECC enable flag + * @stats_lock: Lock for synchronizing hardware stats * @ecc_2bit_rxfifo_cnt: RXFIFO 2bit ECC count * @ecc_1bit_rxfifo_cnt: RXFIFO 1bit ECC count * @ecc_2bit_txolfifo_cnt: TXOLFIFO 2bit ECC count @@ -245,6 +246,7 @@ struct xcan_priv { struct phy *transceiver; struct reset_control *rstc; bool ecc_enable; + spinlock_t stats_lock; /* Lock for synchronizing hardware stats */ u64 ecc_2bit_rxfifo_cnt; u64 ecc_1bit_rxfifo_cnt; u64 ecc_2bit_txolfifo_cnt; @@ -1164,6 +1166,9 @@ static void xcan_err_interrupt(struct net_device *nde= v, u32 isr) =20 if (priv->ecc_enable) { u32 reg_ecc; + unsigned long flags; + + spin_lock_irqsave(&priv->stats_lock, flags); =20 reg_ecc =3D priv->read_reg(priv, XCAN_RXFIFO_ECC_OFFSET); if (isr & XCAN_IXR_E2BERX_MASK) { @@ -1212,6 +1217,8 @@ static void xcan_err_interrupt(struct net_device *nde= v, u32 isr) */ priv->write_reg(priv, XCAN_ECC_CFG_OFFSET, XCAN_ECC_CFG_REECRX_MASK | XCAN_ECC_CFG_REECTXOL_MASK | XCAN_ECC_CFG_REECTXTL_MASK); + + spin_unlock_irqrestore(&priv->stats_lock, flags); } =20 if (cf.can_id) { @@ -1639,6 +1646,23 @@ static int xcan_get_auto_tdcv(const struct net_devic= e *ndev, u32 *tdcv) return 0; } =20 +static void ethtool_get_ethtool_stats(struct net_device *ndev, + struct ethtool_stats *stats, u64 *data) +{ + struct xcan_priv *priv =3D netdev_priv(ndev); + unsigned long flags; + int i =3D 0; + + spin_lock_irqsave(&priv->stats_lock, flags); + data[i++] =3D priv->ecc_2bit_rxfifo_cnt; + data[i++] =3D priv->ecc_1bit_rxfifo_cnt; + data[i++] =3D priv->ecc_2bit_txolfifo_cnt; + data[i++] =3D priv->ecc_1bit_txolfifo_cnt; + data[i++] =3D priv->ecc_2bit_txtlfifo_cnt; + data[i++] =3D priv->ecc_1bit_txtlfifo_cnt; + spin_unlock_irqrestore(&priv->stats_lock, flags); +} + static const struct net_device_ops xcan_netdev_ops =3D { .ndo_open =3D xcan_open, .ndo_stop =3D xcan_close, @@ -1648,6 +1672,7 @@ static const struct net_device_ops xcan_netdev_ops = =3D { =20 static const struct ethtool_ops xcan_ethtool_ops =3D { .get_ts_info =3D ethtool_op_get_ts_info, + .get_ethtool_stats =3D ethtool_get_ethtool_stats, }; =20 /** --=20 2.1.1