From nobody Fri Dec 19 01:41:24 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86A30C83F16 for ; Thu, 31 Aug 2023 01:31:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345563AbjHaBbl (ORCPT ); Wed, 30 Aug 2023 21:31:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44990 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238107AbjHaBbg (ORCPT ); Wed, 30 Aug 2023 21:31:36 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED849CC9; Wed, 30 Aug 2023 18:31:31 -0700 (PDT) Date: Thu, 31 Aug 2023 01:31:29 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1693445489; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xRN44fMksxAydgdcP62P7opSGfW66a4FkW/NtbSw/KA=; b=ozvEaufVuOvnqaUdj22mgj4/k4a7AlA2q9fYS1W7wIfO2UMJ0dTEGwBpDjwmjhEjgiRv6l PH1HG9YHk/XRNJVOMKStF3ApHpQe/hQsbaQbswmwGJ22TWMkfoiSb/Ia4NQ9019mwfv4ws /y2kSINmoHRXalRhGOeOLID/NzLZ8ljjYhVglzeIAb88CBJ9/DIIBq9g1yDYxLuk3LYmrK g2lm9BQEQ9s5T996EQXIWxhSaA19qUxGs2eG/K3cd419s7OJ0dHuFuSCe7RKc5UCpUkeOM 8HtMK+hJZsMSaCtUv/Xc5b3onwGRUjbVSlqkTKZCmmd4lKv5jGptqgg6KaOPkA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1693445489; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xRN44fMksxAydgdcP62P7opSGfW66a4FkW/NtbSw/KA=; b=egu2OwU3Jpe/7gkO87KoWk7ZhbwI5Qaa0Sci6YUpoxG8scJ07AGF5IF3+we1hSYNGuZT5P LuytOWT4S9SFTEAA== From: "tip-bot2 for Mans Rullgard" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: timers/core] clocksource/drivers/sun5i: Convert to platform device driver Cc: Mans Rullgard , Jernej Skrabec , Maxime Ripard , Daniel Lezcano , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20230630201800.16501-4-mans@mansr.com> References: <20230630201800.16501-4-mans@mansr.com> MIME-Version: 1.0 Message-ID: <169344548923.27769.18272995599299715403.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the timers/core branch of tip: Commit-ID: 7e5bac610d2fd4d270adfd2d70ce766df1711bf8 Gitweb: https://git.kernel.org/tip/7e5bac610d2fd4d270adfd2d70ce766df= 1711bf8 Author: Mans Rullgard AuthorDate: Fri, 30 Jun 2023 21:01:28 +01:00 Committer: Daniel Lezcano CommitterDate: Fri, 18 Aug 2023 12:15:22 +02:00 clocksource/drivers/sun5i: Convert to platform device driver Convert the sun5i hstimer driver to a platform device driver. This makes it work again on A20 and other systems where the clock is provided by a platform device driver. Fixes: 7ec03b588d22 ("clk: sunxi-ng: Convert early providers to platform dr= ivers") Signed-off-by: Mans Rullgard Acked-by: Jernej Skrabec Acked-by: Maxime Ripard Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/20230630201800.16501-4-mans@mansr.com --- drivers/clocksource/timer-sun5i.c | 121 ++++++++++++++++------------- 1 file changed, 69 insertions(+), 52 deletions(-) diff --git a/drivers/clocksource/timer-sun5i.c b/drivers/clocksource/timer-= sun5i.c index 3ca427e..69fee35 100644 --- a/drivers/clocksource/timer-sun5i.c +++ b/drivers/clocksource/timer-sun5i.c @@ -16,9 +16,7 @@ #include #include #include -#include -#include -#include +#include =20 #define TIMER_IRQ_EN_REG 0x00 #define TIMER_IRQ_EN(val) BIT(val) @@ -171,10 +169,10 @@ static int sun5i_rate_cb(struct notifier_block *nb, return NOTIFY_DONE; } =20 -static int __init sun5i_setup_clocksource(struct device_node *node, - struct sun5i_timer *cs, - unsigned long rate) +static int sun5i_setup_clocksource(struct platform_device *pdev, + unsigned long rate) { + struct sun5i_timer *cs =3D platform_get_drvdata(pdev); void __iomem *base =3D cs->base; int ret; =20 @@ -182,7 +180,7 @@ static int __init sun5i_setup_clocksource(struct device= _node *node, writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD, base + TIMER_CTL_REG(1)); =20 - cs->clksrc.name =3D node->name; + cs->clksrc.name =3D pdev->dev.of_node->name; cs->clksrc.rating =3D 340; cs->clksrc.read =3D sun5i_clksrc_read; cs->clksrc.mask =3D CLOCKSOURCE_MASK(32); @@ -190,22 +188,23 @@ static int __init sun5i_setup_clocksource(struct devi= ce_node *node, =20 ret =3D clocksource_register_hz(&cs->clksrc, rate); if (ret) { - pr_err("Couldn't register clock source.\n"); + dev_err(&pdev->dev, "Couldn't register clock source.\n"); return ret; } =20 return 0; } =20 -static int __init sun5i_setup_clockevent(struct device_node *node, - struct sun5i_timer *ce, - unsigned long rate, int irq) +static int sun5i_setup_clockevent(struct platform_device *pdev, + unsigned long rate, int irq) { + struct device *dev =3D &pdev->dev; + struct sun5i_timer *ce =3D platform_get_drvdata(pdev); void __iomem *base =3D ce->base; int ret; u32 val; =20 - ce->clkevt.name =3D node->name; + ce->clkevt.name =3D dev->of_node->name; ce->clkevt.features =3D CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; ce->clkevt.set_next_event =3D sun5i_clkevt_next_event; ce->clkevt.set_state_shutdown =3D sun5i_clkevt_shutdown; @@ -223,18 +222,20 @@ static int __init sun5i_setup_clockevent(struct devic= e_node *node, clockevents_config_and_register(&ce->clkevt, rate, TIMER_SYNC_TICKS, 0xffffffff); =20 - ret =3D request_irq(irq, sun5i_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL, - "sun5i_timer0", ce); + ret =3D devm_request_irq(dev, irq, sun5i_timer_interrupt, + IRQF_TIMER | IRQF_IRQPOLL, + "sun5i_timer0", ce); if (ret) { - pr_err("Unable to register interrupt\n"); + dev_err(dev, "Unable to register interrupt\n"); return ret; } =20 return 0; } =20 -static int __init sun5i_timer_init(struct device_node *node) +static int sun5i_timer_probe(struct platform_device *pdev) { + struct device *dev =3D &pdev->dev; struct sun5i_timer *st; struct reset_control *rstc; void __iomem *timer_base; @@ -242,39 +243,34 @@ static int __init sun5i_timer_init(struct device_node= *node) unsigned long rate; int irq, ret; =20 - st =3D kzalloc(sizeof(*st), GFP_KERNEL); + st =3D devm_kzalloc(dev, sizeof(*st), GFP_KERNEL); if (!st) return -ENOMEM; =20 - timer_base =3D of_io_request_and_map(node, 0, of_node_full_name(node)); + platform_set_drvdata(pdev, st); + + timer_base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(timer_base)) { - pr_err("Can't map registers\n"); + dev_err(dev, "Can't map registers\n"); return PTR_ERR(timer_base); } =20 - irq =3D irq_of_parse_and_map(node, 0); - if (irq <=3D 0) { - pr_err("Can't parse IRQ\n"); - return -EINVAL; + irq =3D platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(dev, "Can't get IRQ\n"); + return irq; } =20 - clk =3D of_clk_get(node, 0); + clk =3D devm_clk_get_enabled(dev, NULL); if (IS_ERR(clk)) { - pr_err("Can't get timer clock\n"); + dev_err(dev, "Can't get timer clock\n"); return PTR_ERR(clk); } =20 - ret =3D clk_prepare_enable(clk); - if (ret) { - pr_err("Couldn't enable parent clock\n"); - goto err_free; - } - rate =3D clk_get_rate(clk); if (!rate) { - pr_err("Couldn't get parent clock rate\n"); - ret =3D -EINVAL; - goto err_disable_clk; + dev_err(dev, "Couldn't get parent clock rate\n"); + return -EINVAL; } =20 st->base =3D timer_base; @@ -283,31 +279,52 @@ static int __init sun5i_timer_init(struct device_node= *node) st->clk_rate_cb.notifier_call =3D sun5i_rate_cb; st->clk_rate_cb.next =3D NULL; =20 - ret =3D clk_notifier_register(clk, &st->clk_rate_cb); + ret =3D devm_clk_notifier_register(dev, clk, &st->clk_rate_cb); if (ret) { - pr_err("Unable to register clock notifier.\n"); - goto err_disable_clk; + dev_err(dev, "Unable to register clock notifier.\n"); + return ret; } =20 - rstc =3D of_reset_control_get(node, NULL); - if (!IS_ERR(rstc)) + rstc =3D devm_reset_control_get_optional_exclusive(dev, NULL); + if (rstc) reset_control_deassert(rstc); =20 - ret =3D sun5i_setup_clocksource(node, st, rate); + ret =3D sun5i_setup_clocksource(pdev, rate); + if (ret) + return ret; + + ret =3D sun5i_setup_clockevent(pdev, rate, irq); if (ret) - goto err_remove_notifier; + goto err_unreg_clocksource; =20 - return sun5i_setup_clockevent(node, st, rate, irq); + return 0; =20 -err_remove_notifier: - clk_notifier_unregister(clk, &st->clk_rate_cb); -err_disable_clk: - clk_disable_unprepare(clk); -err_free: - kfree(st); +err_unreg_clocksource: + clocksource_unregister(&st->clksrc); return ret; } -TIMER_OF_DECLARE(sun5i_a13, "allwinner,sun5i-a13-hstimer", - sun5i_timer_init); -TIMER_OF_DECLARE(sun7i_a20, "allwinner,sun7i-a20-hstimer", - sun5i_timer_init); + +static void sun5i_timer_remove(struct platform_device *pdev) +{ + struct sun5i_timer *st =3D platform_get_drvdata(pdev); + + clocksource_unregister(&st->clksrc); +} + +static const struct of_device_id sun5i_timer_of_match[] =3D { + { .compatible =3D "allwinner,sun5i-a13-hstimer" }, + { .compatible =3D "allwinner,sun7i-a20-hstimer" }, + {}, +}; +MODULE_DEVICE_TABLE(of, sun5i_timer_of_match); + +static struct platform_driver sun5i_timer_driver =3D { + .probe =3D sun5i_timer_probe, + .remove_new =3D sun5i_timer_remove, + .driver =3D { + .name =3D "sun5i-timer", + .of_match_table =3D sun5i_timer_of_match, + .suppress_bind_attrs =3D true, + }, +}; +module_platform_driver(sun5i_timer_driver);