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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2023 10:45:54.0856 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2ee6bd41-e451-480e-9d62-08dba2fcf5c6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7804 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ECC feature added to Tx and Rx FIFO=E2=80=99s for Xilinx CAN Controller. Part of this feature configuration and counter registers added in IP for 1bit/2bit ECC errors. xlnx,has-ecc is optional property and added to Xilinx CAN Controller node if ECC block enabled in the HW Signed-off-by: Srinivas Goud --- Documentation/devicetree/bindings/net/can/xilinx,can.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml b/Do= cumentation/devicetree/bindings/net/can/xilinx,can.yaml index 64d57c3..c842610 100644 --- a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml +++ b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml @@ -49,6 +49,10 @@ properties: resets: maxItems: 1 =20 + xlnx,has-ecc: + $ref: /schemas/types.yaml#/definitions/flag + description: CAN Tx and Rx fifo ECC enable flag (AXI CAN) + required: - compatible - reg @@ -137,6 +141,7 @@ examples: interrupts =3D ; tx-fifo-depth =3D <0x40>; rx-fifo-depth =3D <0x40>; + xlnx,has-ecc }; =20 - | --=20 2.1.1 From nobody Wed Dec 17 09:17:00 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5684EEE49AB for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2023 10:45:58.8974 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6ee2c12a-e6a4-433d-75e8-08dba2fcf8a2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9DC.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5120 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add ECC support for Xilinx CAN Controller, so this driver reports 1bit/2bit ECC errors for FIFO's based on ECC error interrupt. ECC feature for Xilinx CAN Controller selected through 'xlnx,has-ecc' DT property Signed-off-by: Srinivas Goud --- drivers/net/can/xilinx_can.c | 129 ++++++++++++++++++++++++++++++++++++++-= ---- 1 file changed, 114 insertions(+), 15 deletions(-) diff --git a/drivers/net/can/xilinx_can.c b/drivers/net/can/xilinx_can.c index abe58f1..798b32b 100644 --- a/drivers/net/can/xilinx_can.c +++ b/drivers/net/can/xilinx_can.c @@ -53,18 +53,23 @@ enum xcan_reg { XCAN_AFR_OFFSET =3D 0x60, /* Acceptance Filter */ =20 /* only on CAN FD cores */ - XCAN_F_BRPR_OFFSET =3D 0x088, /* Data Phase Baud Rate - * Prescaler - */ - XCAN_F_BTR_OFFSET =3D 0x08C, /* Data Phase Bit Timing */ - XCAN_TRR_OFFSET =3D 0x0090, /* TX Buffer Ready Request */ - XCAN_AFR_EXT_OFFSET =3D 0x00E0, /* Acceptance Filter */ - XCAN_FSR_OFFSET =3D 0x00E8, /* RX FIFO Status */ - XCAN_TXMSG_BASE_OFFSET =3D 0x0100, /* TX Message Space */ + XCAN_F_BRPR_OFFSET =3D 0x88, /* Data Phase Baud Rate Prescaler */ + XCAN_F_BTR_OFFSET =3D 0x8C, /* Data Phase Bit Timing */ + XCAN_TRR_OFFSET =3D 0x90, /* TX Buffer Ready Request */ + + /* only on AXI CAN cores */ + XCAN_ECC_CFG_OFFSET =3D 0xC8, /* ECC Configuration */ + XCAN_TXTLFIFO_ECC_OFFSET =3D 0xCC, /* TXTL FIFO ECC error counter = */ + XCAN_TXOLFIFO_ECC_OFFSET =3D 0xD0, /* TXOL FIFO ECC error counter = */ + XCAN_RXFIFO_ECC_OFFSET =3D 0xD4, /* RX FIFO ECC error counter */ + + XCAN_AFR_EXT_OFFSET =3D 0xE0, /* Acceptance Filter */ + XCAN_FSR_OFFSET =3D 0xE8, /* RX FIFO Status */ + XCAN_TXMSG_BASE_OFFSET =3D 0x100, /* TX Message Space */ + XCAN_AFR_2_MASK_OFFSET =3D 0xA00, /* Acceptance Filter MASK */ + XCAN_AFR_2_ID_OFFSET =3D 0xA04, /* Acceptance Filter ID */ XCAN_RXMSG_BASE_OFFSET =3D 0x1100, /* RX Message Space */ XCAN_RXMSG_2_BASE_OFFSET =3D 0x2100, /* RX Message Space */ - XCAN_AFR_2_MASK_OFFSET =3D 0x0A00, /* Acceptance Filter MASK */ - XCAN_AFR_2_ID_OFFSET =3D 0x0A04, /* Acceptance Filter ID */ }; =20 #define XCAN_FRAME_ID_OFFSET(frame_base) ((frame_base) + 0x00) @@ -124,6 +129,12 @@ enum xcan_reg { #define XCAN_IXR_TXFLL_MASK 0x00000004 /* Tx FIFO Full intr */ #define XCAN_IXR_TXOK_MASK 0x00000002 /* TX successful intr */ #define XCAN_IXR_ARBLST_MASK 0x00000001 /* Arbitration lost intr */ +#define XCAN_IXR_E2BERX_MASK BIT(23) /* RX FIFO two bit ECC err= or */ +#define XCAN_IXR_E1BERX_MASK BIT(22) /* RX FIFO one bit ECC err= or */ +#define XCAN_IXR_E2BETXOL_MASK BIT(21) /* TXOL FIFO two bit ECC e= rror */ +#define XCAN_IXR_E1BETXOL_MASK BIT(20) /* TXOL FIFO One bit ECC e= rror */ +#define XCAN_IXR_E2BETXTL_MASK BIT(19) /* TXTL FIFO Two bit ECC e= rror */ +#define XCAN_IXR_E1BETXTL_MASK BIT(18) /* TXTL FIFO One bit ECC e= rror */ #define XCAN_IDR_ID1_MASK 0xFFE00000 /* Standard msg identifier */ #define XCAN_IDR_SRR_MASK 0x00100000 /* Substitute remote TXreq */ #define XCAN_IDR_IDE_MASK 0x00080000 /* Identifier extension */ @@ -137,6 +148,11 @@ enum xcan_reg { #define XCAN_2_FSR_RI_MASK 0x0000003F /* RX Read Index */ #define XCAN_DLCR_EDL_MASK 0x08000000 /* EDL Mask in DLC */ #define XCAN_DLCR_BRS_MASK 0x04000000 /* BRS Mask in DLC */ +#define XCAN_ECC_CFG_REECRX_MASK BIT(2) /* Reset RX FIFO ECC error counter= s */ +#define XCAN_ECC_CFG_REECTXOL_MASK BIT(1) /* Reset TXOL FIFO ECC error cou= nters */ +#define XCAN_ECC_CFG_REECTXTL_MASK BIT(0) /* Reset TXTL FIFO ECC error cou= nters */ +#define XCAN_ECC_1BIT_CNT_MASK GENMASK(15, 0) /* FIFO ECC 1bit count mask= */ +#define XCAN_ECC_2BIT_CNT_MASK GENMASK(31, 16) /* FIFO ECC 2bit count mas= k */ =20 /* CAN register bit shift - XCAN___SHIFT */ #define XCAN_BRPR_TDC_ENABLE BIT(16) /* Transmitter Delay Compensation (T= DC) Enable */ @@ -202,6 +218,13 @@ struct xcan_devtype_data { * @devtype: Device type specific constants * @transceiver: Optional pointer to associated CAN transceiver * @rstc: Pointer to reset control + * @ecc_enable: ECC enable flag + * @ecc_2bit_rxfifo_cnt: RXFIFO 2bit ECC count + * @ecc_1bit_rxfifo_cnt: RXFIFO 1bit ECC count + * @ecc_2bit_txolfifo_cnt: TXOLFIFO 2bit ECC count + * @ecc_1bit_txolfifo_cnt: TXOLFIFO 1bit ECC count + * @ecc_2bit_txtlfifo_cnt: TXTLFIFO 2bit ECC count + * @ecc_1bit_txtlfifo_cnt: TXTLFIFO 1bit ECC count */ struct xcan_priv { struct can_priv can; @@ -221,6 +244,13 @@ struct xcan_priv { struct xcan_devtype_data devtype; struct phy *transceiver; struct reset_control *rstc; + bool ecc_enable; + u64 ecc_2bit_rxfifo_cnt; + u64 ecc_1bit_rxfifo_cnt; + u64 ecc_2bit_txolfifo_cnt; + u64 ecc_1bit_txolfifo_cnt; + u64 ecc_2bit_txtlfifo_cnt; + u64 ecc_1bit_txtlfifo_cnt; }; =20 /* CAN Bittiming constants as per Xilinx CAN specs */ @@ -523,6 +553,11 @@ static int xcan_chip_start(struct net_device *ndev) XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK | XCAN_IXR_ARBLST_MASK | xcan_rx_int_mask(priv); =20 + if (priv->ecc_enable) + ier |=3D XCAN_IXR_E2BERX_MASK | XCAN_IXR_E1BERX_MASK | + XCAN_IXR_E2BETXOL_MASK | XCAN_IXR_E1BETXOL_MASK | + XCAN_IXR_E2BETXTL_MASK | XCAN_IXR_E1BETXTL_MASK; + if (priv->devtype.flags & XCAN_FLAG_RXMNF) ier |=3D XCAN_IXR_RXMNF_MASK; =20 @@ -1127,6 +1162,58 @@ static void xcan_err_interrupt(struct net_device *nd= ev, u32 isr) priv->can.can_stats.bus_error++; } =20 + if (priv->ecc_enable) { + u32 reg_ecc; + + reg_ecc =3D priv->read_reg(priv, XCAN_RXFIFO_ECC_OFFSET); + if (isr & XCAN_IXR_E2BERX_MASK) { + priv->ecc_2bit_rxfifo_cnt +=3D + FIELD_GET(XCAN_ECC_2BIT_CNT_MASK, reg_ecc); + netdev_dbg(ndev, "%s: RX FIFO 2bit ECC error count %lld\n", + __func__, priv->ecc_2bit_rxfifo_cnt); + } + if (isr & XCAN_IXR_E1BERX_MASK) { + priv->ecc_1bit_rxfifo_cnt +=3D + FIELD_GET(XCAN_ECC_1BIT_CNT_MASK, reg_ecc); + netdev_dbg(ndev, "%s: RX FIFO 1bit ECC error count %lld\n", + __func__, priv->ecc_1bit_rxfifo_cnt); + } + + reg_ecc =3D priv->read_reg(priv, XCAN_TXOLFIFO_ECC_OFFSET); + if (isr & XCAN_IXR_E2BETXOL_MASK) { + priv->ecc_2bit_txolfifo_cnt +=3D + FIELD_GET(XCAN_ECC_2BIT_CNT_MASK, reg_ecc); + netdev_dbg(ndev, "%s: TXOL FIFO 2bit ECC error count %lld\n", + __func__, priv->ecc_2bit_txolfifo_cnt); + } + if (isr & XCAN_IXR_E1BETXOL_MASK) { + priv->ecc_1bit_txolfifo_cnt +=3D + FIELD_GET(XCAN_ECC_1BIT_CNT_MASK, reg_ecc); + netdev_dbg(ndev, "%s: TXOL FIFO 1bit ECC error count %lld\n", + __func__, priv->ecc_1bit_txolfifo_cnt); + } + + reg_ecc =3D priv->read_reg(priv, XCAN_TXTLFIFO_ECC_OFFSET); + if (isr & XCAN_IXR_E2BETXTL_MASK) { + priv->ecc_2bit_txtlfifo_cnt +=3D + FIELD_GET(XCAN_ECC_2BIT_CNT_MASK, reg_ecc); + netdev_dbg(ndev, "%s: TXTL FIFO 2bit ECC error count %lld\n", + __func__, priv->ecc_2bit_txtlfifo_cnt); + } + if (isr & XCAN_IXR_E1BETXTL_MASK) { + priv->ecc_1bit_txtlfifo_cnt +=3D + FIELD_GET(XCAN_ECC_1BIT_CNT_MASK, reg_ecc); + netdev_dbg(ndev, "%s: TXTL FIFO 1bit ECC error count %lld\n", + __func__, priv->ecc_1bit_txtlfifo_cnt); + } + + /* The counter reaches its maximum at 0xffff and does not overflow. + * Accept the small race window between reading and resetting ECC counte= rs. + */ + priv->write_reg(priv, XCAN_ECC_CFG_OFFSET, XCAN_ECC_CFG_REECRX_MASK | + XCAN_ECC_CFG_REECTXOL_MASK | XCAN_ECC_CFG_REECTXTL_MASK); + } + if (cf.can_id) { struct can_frame *skb_cf; struct sk_buff *skb =3D alloc_can_err_skb(ndev, &skb_cf); @@ -1354,9 +1441,8 @@ static irqreturn_t xcan_interrupt(int irq, void *dev_= id) { struct net_device *ndev =3D (struct net_device *)dev_id; struct xcan_priv *priv =3D netdev_priv(ndev); - u32 isr, ier; - u32 isr_errors; u32 rx_int_mask =3D xcan_rx_int_mask(priv); + u32 isr, ier, isr_errors, mask; =20 /* Get the interrupt status from Xilinx CAN */ isr =3D priv->read_reg(priv, XCAN_ISR_OFFSET); @@ -1374,10 +1460,17 @@ static irqreturn_t xcan_interrupt(int irq, void *de= v_id) if (isr & XCAN_IXR_TXOK_MASK) xcan_tx_interrupt(ndev, isr); =20 + mask =3D XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK | + XCAN_IXR_BSOFF_MASK | XCAN_IXR_ARBLST_MASK | + XCAN_IXR_RXMNF_MASK; + + if (priv->ecc_enable) + mask |=3D XCAN_IXR_E2BERX_MASK | XCAN_IXR_E1BERX_MASK | + XCAN_IXR_E2BETXOL_MASK | XCAN_IXR_E1BETXOL_MASK | + XCAN_IXR_E2BETXTL_MASK | XCAN_IXR_E1BETXTL_MASK; + /* Check for the type of error interrupt and Processing it */ - isr_errors =3D isr & (XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK | - XCAN_IXR_BSOFF_MASK | XCAN_IXR_ARBLST_MASK | - XCAN_IXR_RXMNF_MASK); + isr_errors =3D isr & mask; if (isr_errors) { priv->write_reg(priv, XCAN_ICR_OFFSET, isr_errors); xcan_err_interrupt(ndev, isr); @@ -1796,6 +1889,7 @@ static int xcan_probe(struct platform_device *pdev) return -ENOMEM; =20 priv =3D netdev_priv(ndev); + priv->ecc_enable =3D of_property_read_bool(pdev->dev.of_node, "xlnx,has-e= cc"); priv->dev =3D &pdev->dev; priv->can.bittiming_const =3D devtype->bittiming_const; priv->can.do_set_mode =3D xcan_do_set_mode; @@ -1912,6 +2006,11 @@ static int xcan_probe(struct platform_device *pdev) priv->reg_base, ndev->irq, priv->can.clock.freq, hw_tx_max, priv->tx_max); =20 + if (priv->ecc_enable) { + /* Reset FIFO ECC counters */ + priv->write_reg(priv, XCAN_ECC_CFG_OFFSET, XCAN_ECC_CFG_REECRX_MASK | + XCAN_ECC_CFG_REECTXOL_MASK | XCAN_ECC_CFG_REECTXTL_MASK); + } return 0; =20 err_disableclks: --=20 2.1.1 From nobody Wed Dec 17 09:17:00 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5BB3EE49A3 for ; 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Tue, 22 Aug 2023 05:45:58 -0500 From: Srinivas Goud To: , , , , , , , , , CC: , , , , , , Srinivas Goud Subject: [PATCH v2 3/3] can: xilinx_can: Add ethtool stats interface for ECC errors Date: Tue, 22 Aug 2023 16:15:36 +0530 Message-ID: <1692701136-1422086-4-git-send-email-srinivas.goud@amd.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1692701136-1422086-1-git-send-email-srinivas.goud@amd.com> References: <1692701136-1422086-1-git-send-email-srinivas.goud@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D6:EE_|SJ2PR12MB8011:EE_ X-MS-Office365-Filtering-Correlation-Id: d893352a-dbbb-4e01-aa55-08dba2fcfb9e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Q5AKvmDQUfcGJ5+2AKDo5ize/YJbaqNnwMqXacLRfevOGByM9io6aFQIuYbUeJN3OKWdCcbYkIDYrf5OGkiYh4SWd2v8GvILqkcua9uo5jyj8nZOY+xP0BwDGbW8Nqmllx0hDkXso066Rai97L87moMJRv4D0tvDh729mcjHcC858Ey+S8GEZGvVgSzG0uDEx4oZDLY52Wwqszw9qo7AxfSmToxNxS39hg98EAPxEuqt8mxxywpKI5n8s2rchiixQJfraVuB194i/GxQIcEwVW7o2ZlIFaBRY5kconDq0HvrfVCAxOLGjQVk3gHwND9MfwgjGWSv1/v6ngm1n/WMYl1IHKERNGy71GYCZVZKZG6cJJtpTZg1plVE1gP+LRwq4ZCz0fsQEEV01YVC9LeTZ/LwZSRVSQDMtwpVLcshdyQSJpiErAANqq1qwZgBsh8bVxBYFZX7WwQXNio/yypxW/CwXlOaEG/43vO7TNsg3zj3awTMWzV+IvgsdMRGfXPYGzw77a4pQF4xKbw1w6FTYoej/PvVTiIcsJMJTBo61PwaDDSEb+IoL3jwqs9f/rSjbnl4SvoTgg2ikggIHUe88rmp6aimop657x5o7spWEh0ktsoegeUWfOOySP5DU8ZA9Y1S5E4vQkPl9WD/DnykhiP2r0suhsT9irSknp8gAhO5U+JdrqcF3eK0T/WHlPZlF1kxwyO5V1QkOrkLIe+8Xu41LYPJaKKaiHdLQcCGxkQ6rGA5FwhgUem5cgcSvpjxtIv6o0K1xzwHlRDR+/gdcXHg1pNuMT0L2xnUB0lovPI= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(346002)(136003)(396003)(376002)(82310400011)(451199024)(1800799009)(186009)(40470700004)(46966006)(36840700001)(356005)(40460700003)(921005)(316002)(478600001)(70206006)(47076005)(36860700001)(426003)(336012)(26005)(6666004)(2906002)(44832011)(4326008)(2616005)(83380400001)(5660300002)(8936002)(8676002)(7416002)(110136005)(70586007)(41300700001)(54906003)(82740400003)(36756003)(86362001)(81166007)(40480700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2023 10:46:03.9057 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d893352a-dbbb-4e01-aa55-08dba2fcfb9e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D6.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8011 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add ethtool stats interface for reading FIFO 1bit/2bit ECC errors information. Signed-off-by: Srinivas Goud --- drivers/net/can/xilinx_can.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/net/can/xilinx_can.c b/drivers/net/can/xilinx_can.c index 798b32b..50e0c9d 100644 --- a/drivers/net/can/xilinx_can.c +++ b/drivers/net/can/xilinx_can.c @@ -219,6 +219,7 @@ struct xcan_devtype_data { * @transceiver: Optional pointer to associated CAN transceiver * @rstc: Pointer to reset control * @ecc_enable: ECC enable flag + * @stats_lock: Lock for synchronizing hardware stats * @ecc_2bit_rxfifo_cnt: RXFIFO 2bit ECC count * @ecc_1bit_rxfifo_cnt: RXFIFO 1bit ECC count * @ecc_2bit_txolfifo_cnt: TXOLFIFO 2bit ECC count @@ -245,6 +246,7 @@ struct xcan_priv { struct phy *transceiver; struct reset_control *rstc; bool ecc_enable; + spinlock_t stats_lock; /* Lock for synchronizing hardware stats */ u64 ecc_2bit_rxfifo_cnt; u64 ecc_1bit_rxfifo_cnt; u64 ecc_2bit_txolfifo_cnt; @@ -1164,6 +1166,9 @@ static void xcan_err_interrupt(struct net_device *nde= v, u32 isr) =20 if (priv->ecc_enable) { u32 reg_ecc; + unsigned long flags; + + spin_lock_irqsave(&priv->stats_lock, flags); =20 reg_ecc =3D priv->read_reg(priv, XCAN_RXFIFO_ECC_OFFSET); if (isr & XCAN_IXR_E2BERX_MASK) { @@ -1212,6 +1217,8 @@ static void xcan_err_interrupt(struct net_device *nde= v, u32 isr) */ priv->write_reg(priv, XCAN_ECC_CFG_OFFSET, XCAN_ECC_CFG_REECRX_MASK | XCAN_ECC_CFG_REECTXOL_MASK | XCAN_ECC_CFG_REECTXTL_MASK); + + spin_unlock_irqrestore(&priv->stats_lock, flags); } =20 if (cf.can_id) { @@ -1639,6 +1646,23 @@ static int xcan_get_auto_tdcv(const struct net_devic= e *ndev, u32 *tdcv) return 0; } =20 +static void ethtool_get_ethtool_stats(struct net_device *ndev, + struct ethtool_stats *stats, u64 *data) +{ + struct xcan_priv *priv =3D netdev_priv(ndev); + unsigned long flags; + int i =3D 0; + + spin_lock_irqsave(&priv->stats_lock, flags); + data[i++] =3D priv->ecc_2bit_rxfifo_cnt; + data[i++] =3D priv->ecc_1bit_rxfifo_cnt; + data[i++] =3D priv->ecc_2bit_txolfifo_cnt; + data[i++] =3D priv->ecc_1bit_txolfifo_cnt; + data[i++] =3D priv->ecc_2bit_txtlfifo_cnt; + data[i++] =3D priv->ecc_1bit_txtlfifo_cnt; + spin_unlock_irqrestore(&priv->stats_lock, flags); +} + static const struct net_device_ops xcan_netdev_ops =3D { .ndo_open =3D xcan_open, .ndo_stop =3D xcan_close, @@ -1648,6 +1672,7 @@ static const struct net_device_ops xcan_netdev_ops = =3D { =20 static const struct ethtool_ops xcan_ethtool_ops =3D { .get_ts_info =3D ethtool_op_get_ts_info, + .get_ethtool_stats =3D ethtool_get_ethtool_stats, }; =20 /** --=20 2.1.1