From nobody Fri Sep 12 03:18:50 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED45FC001E0 for ; Wed, 9 Aug 2023 16:49:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231623AbjHIQtw (ORCPT ); Wed, 9 Aug 2023 12:49:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51602 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231286AbjHIQte (ORCPT ); Wed, 9 Aug 2023 12:49:34 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 844F91FCC; Wed, 9 Aug 2023 09:49:33 -0700 (PDT) Date: Wed, 09 Aug 2023 16:49:31 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691599772; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=OFs3NMhd5gzi5ueDtVWTqkP7VuFvuvi5oFckrMFgPnM=; b=f1VCqKNME+BfIRUb9nTJB8Q4f8lAoBQlWxR9lhCzKRhr4dyAtvgR+fgqqAcw61E3MOh81h hKY3fxtTSB1xsNUmj+KjU7ZFgKNl3GyWEWW57r5bSiMgfJtKoq6m1zwxwMCKnziRdINecW F34PO1mNH9CbS4KcTqfVKeyb4N7iCM3ZhZqmM+VnaJ/2CtSQbB552EOHVPr6HUVp3jUYBJ KswZRgf6pX7iZ1leo3ny24LH0WMXg0IHdbXMViE1lQWYHkf2gmz86g+zJJpGfxd0obQ2jU Ze3VXDYUE76mNeiEzDlxhCeYy42H/GCPt/2kvjl/RwDoFQBp3h0PX92gDQk6+g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691599772; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=OFs3NMhd5gzi5ueDtVWTqkP7VuFvuvi5oFckrMFgPnM=; b=O1E07jyxsPVmxRW6SKbORI+lsLY7+uICgccHm/JXLjEySCq6SazT9mTCrBjDj0mMYWeBRK Geg0fznMUgohlqAA== From: "tip-bot2 for Thomas Gleixner" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/apic] x86/apic/ipi: Tidy up the code and fixup comments Cc: Thomas Gleixner , Dave Hansen , "Peter Zijlstra (Intel)" , x86@kernel.org, linux-kernel@vger.kernel.org MIME-Version: 1.0 Message-ID: <169159977164.27769.5654893944215049912.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the x86/apic branch of tip: Commit-ID: 1584514b72d612abd3343e98167fc09033e208d9 Gitweb: https://git.kernel.org/tip/1584514b72d612abd3343e98167fc0903= 3e208d9 Author: Thomas Gleixner AuthorDate: Tue, 08 Aug 2023 15:04:03 -07:00 Committer: Dave Hansen CommitterDate: Wed, 09 Aug 2023 08:10:12 -07:00 x86/apic/ipi: Tidy up the code and fixup comments Replace the undecodable comment on top of the function, replace the space consuming zero content comments with useful ones and tidy up the implementation to prevent further eye bleed. Make __default_send_IPI_shortcut() static as it has no other users. Signed-off-by: Thomas Gleixner Signed-off-by: Dave Hansen Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/ipi.c | 74 +++++++++++++++-------------------- arch/x86/kernel/apic/local.h | 2 +- 2 files changed, 32 insertions(+), 44 deletions(-) diff --git a/arch/x86/kernel/apic/ipi.c b/arch/x86/kernel/apic/ipi.c index 2ff9cf9..614ac55 100644 --- a/arch/x86/kernel/apic/ipi.c +++ b/arch/x86/kernel/apic/ipi.c @@ -108,68 +108,58 @@ static inline void __xapic_wait_icr_idle(void) cpu_relax(); } =20 -void __default_send_IPI_shortcut(unsigned int shortcut, int vector) +/* + * This is safe against interruption because it only writes the lower 32 + * bits of the APIC_ICR register. The destination field is ignored for + * short hand IPIs. + * + * wait_icr_idle() + * write(ICR2, dest) + * NMI + * wait_icr_idle() + * write(ICR) + * wait_icr_idle() + * write(ICR) + * + * This function does not need to disable interrupts as there is no ICR2 + * interaction. The memory write is direct except when the machine is + * affected by the 11AP Pentium erratum, which turns the plain write into + * an XCHG operation. + */ +static void __default_send_IPI_shortcut(unsigned int shortcut, int vector) { /* - * Subtle. In the case of the 'never do double writes' workaround - * we have to lock out interrupts to be safe. As we don't care - * of the value read we use an atomic rmw access to avoid costly - * cli/sti. Otherwise we use an even cheaper single atomic write - * to the APIC. - */ - unsigned int cfg; - - /* - * Wait for idle. + * Wait for the previous ICR command to complete. Use + * safe_apic_wait_icr_idle() for the NMI vector as there have been + * issues where otherwise the system hangs when the panic CPU tries + * to stop the others before launching the kdump kernel. */ if (unlikely(vector =3D=3D NMI_VECTOR)) safe_apic_wait_icr_idle(); else __xapic_wait_icr_idle(); =20 - /* - * No need to touch the target chip field. Also the destination - * mode is ignored when a shorthand is used. - */ - cfg =3D __prepare_ICR(shortcut, vector, 0); - - /* - * Send the IPI. The write to APIC_ICR fires this off. - */ - native_apic_mem_write(APIC_ICR, cfg); + /* Destination field (ICR2) and the destination mode are ignored */ + native_apic_mem_write(APIC_ICR, __prepare_ICR(shortcut, vector, 0)); } =20 /* * This is used to send an IPI with no shorthand notation (the destination= is * specified in bits 56 to 63 of the ICR). */ -void __default_send_IPI_dest_field(unsigned int mask, int vector, unsigned= int dest) +void __default_send_IPI_dest_field(unsigned int dest_mask, int vector, + unsigned int dest_mode) { - unsigned long cfg; - - /* - * Wait for idle. - */ + /* See comment in __default_send_IPI_shortcut() */ if (unlikely(vector =3D=3D NMI_VECTOR)) safe_apic_wait_icr_idle(); else __xapic_wait_icr_idle(); =20 - /* - * prepare target chip field - */ - cfg =3D __prepare_ICR2(mask); - native_apic_mem_write(APIC_ICR2, cfg); - - /* - * program the ICR - */ - cfg =3D __prepare_ICR(0, vector, dest); - - /* - * Send the IPI. The write to APIC_ICR fires this off. - */ - native_apic_mem_write(APIC_ICR, cfg); + /* Set the IPI destination field in the ICR */ + native_apic_mem_write(APIC_ICR2, __prepare_ICR2(dest_mask)); + /* Send it with the proper destination mode */ + native_apic_mem_write(APIC_ICR, __prepare_ICR(0, vector, dest_mode)); } =20 void default_send_IPI_single_phys(int cpu, int vector) diff --git a/arch/x86/kernel/apic/local.h b/arch/x86/kernel/apic/local.h index 0c47711..5b0a0e7 100644 --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -44,8 +44,6 @@ static inline unsigned int __prepare_ICR(unsigned int sho= rtcut, int vector, =20 void default_init_apic_ldr(void); =20 -void __default_send_IPI_shortcut(unsigned int shortcut, int vector); - /* * This is used to send an IPI with no shorthand notation (the destination= is * specified in bits 56 to 63 of the ICR).