From nobody Sun Feb 8 21:21:25 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 463F0C001B0 for ; Wed, 9 Aug 2023 15:34:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234415AbjHIPeq (ORCPT ); Wed, 9 Aug 2023 11:34:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57164 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233646AbjHIPeU (ORCPT ); Wed, 9 Aug 2023 11:34:20 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 73F47211C; Wed, 9 Aug 2023 08:34:18 -0700 (PDT) Date: Wed, 09 Aug 2023 15:34:16 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691595257; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=vz4jZNt8zTHzD5vYo/YtlXaX6AlesgnUXySu86WG9sI=; b=kfIZ76VD/zjgXYWSPkXUmr03lbVPuIY0Bd05eGdAOggZgsJQZ+LZQIOdFH7nHog71sSvQp eUJ1uvkqVoHiafh/qzQdfU8u3GX4iAB2XBhoCtKT2mGVipnV9iYZJ/V5mmcFXEuE+OwlmE qAojfE6wgG5No9KdjjhIQ4k/NQk2HBI5WyslzUGOBoktLWh1/+v61SMSqDIVc/Y2DzpaV2 ZBCBKL/dPI0yJWGcaZbiLmlssjT7z9DNXbQhm80IkibLKu/1j44IFa59vUOj4KKh/lRKrI Lo6UCl5mEqa2GTc53pU9C7Ths+gjDdHAVx2xBceKMEvYwU150bNHEvhm/UJlLw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691595257; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=vz4jZNt8zTHzD5vYo/YtlXaX6AlesgnUXySu86WG9sI=; b=VjTDgxxRWK461+RvNXSSQaT4NafMJ8D+/uAoKzVFYp51A+O5kI+ulpYGFcOcR8/EZ0uFnk LdL8F0sWfmfwX/Dw== From: "tip-bot2 for Thomas Gleixner" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/apic] x86/apic: Register boot CPU APIC early Cc: Thomas Gleixner , Dave Hansen , "Peter Zijlstra (Intel)" , x86@kernel.org, linux-kernel@vger.kernel.org MIME-Version: 1.0 Message-ID: <169159525660.27769.2175813055429554939.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the x86/apic branch of tip: Commit-ID: 4b57e1e4f266ae132a24aa4fc3d2a9beb12d13a9 Gitweb: https://git.kernel.org/tip/4b57e1e4f266ae132a24aa4fc3d2a9beb= 12d13a9 Author: Thomas Gleixner AuthorDate: Tue, 08 Aug 2023 15:03:46 -07:00 Committer: Dave Hansen CommitterDate: Wed, 09 Aug 2023 08:10:11 -07:00 x86/apic: Register boot CPU APIC early Register the boot CPU APIC right when the boot CPUs APIC is read from the hardware. No point is doing this on random places and having wild heuristics to save the boot CPU APIC ID slot and CPU number 0 reserved. Signed-off-by: Thomas Gleixner Signed-off-by: Dave Hansen Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/apic.c | 120 ++++++++++++++--------------------- 1 file changed, 50 insertions(+), 70 deletions(-) diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index e26447a..b7ffae4 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -1734,6 +1734,8 @@ void apic_ap_setup(void) end_local_APIC_setup(); } =20 +static __init void cpu_set_boot_apic(void); + static __init void apic_read_boot_cpu_id(bool x2apic) { /* @@ -1748,9 +1750,9 @@ static __init void apic_read_boot_cpu_id(bool x2apic) boot_cpu_physical_apicid =3D read_apic_id(); boot_cpu_apic_version =3D GET_APIC_VERSION(apic_read(APIC_LVR)); } + cpu_set_boot_apic(); } =20 - #ifdef CONFIG_X86_X2APIC int x2apic_mode; EXPORT_SYMBOL_GPL(x2apic_mode); @@ -2426,76 +2428,8 @@ static int allocate_logical_cpuid(int apicid) return nr_logical_cpuids++; } =20 -int generic_processor_info(int apicid, int version) +static void cpu_update_apic(int cpu, int apicid, int version) { - int cpu, max =3D nr_cpu_ids; - bool boot_cpu_detected =3D physid_isset(boot_cpu_physical_apicid, - phys_cpu_present_map); - - /* - * boot_cpu_physical_apicid is guaranteed to contain the boot CPU - * APIC ID read from the local APIC when this function is invoked. - */ - if (disabled_cpu_apicid !=3D boot_cpu_physical_apicid && - disabled_cpu_apicid =3D=3D apicid) { - int thiscpu =3D num_processors + disabled_cpus; - - pr_warn("APIC: Disabling requested cpu. Processor %d/0x%x ignored.\n", - thiscpu, apicid); - - disabled_cpus++; - return -ENODEV; - } - - /* - * If boot cpu has not been detected yet, then only allow upto - * nr_cpu_ids - 1 processors and keep one slot free for boot cpu - */ - if (!boot_cpu_detected && num_processors >=3D nr_cpu_ids - 1 && - apicid !=3D boot_cpu_physical_apicid) { - int thiscpu =3D max + disabled_cpus - 1; - - pr_warn("APIC: NR_CPUS/possible_cpus limit of %i almost" - " reached. Keeping one slot for boot cpu." - " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); - - disabled_cpus++; - return -ENODEV; - } - - if (num_processors >=3D nr_cpu_ids) { - int thiscpu =3D max + disabled_cpus; - - pr_warn("APIC: NR_CPUS/possible_cpus limit of %i reached. " - "Processor %d/0x%x ignored.\n", max, thiscpu, apicid); - - disabled_cpus++; - return -EINVAL; - } - - if (apicid =3D=3D boot_cpu_physical_apicid) { - /* - * x86_cpu_to_apicid is required to have processors listed - * in same order as logical cpu numbers. Hence the first - * entry is BSP, and so on. - * boot_cpu_init() already hold bit 0 in cpu_present_mask - * for BSP. - */ - cpu =3D 0; - - /* Logical cpuid 0 is reserved for BSP. */ - cpuid_to_apicid[0] =3D apicid; - } else { - cpu =3D allocate_logical_cpuid(apicid); - if (cpu < 0) { - disabled_cpus++; - return -EINVAL; - } - } - - /* - * Validate version - */ if (version =3D=3D 0x0) { pr_warn("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\= n", cpu, apicid); @@ -2521,10 +2455,56 @@ int generic_processor_info(int apicid, int version) =20 if (system_state !=3D SYSTEM_BOOTING) cpu_mark_primary_thread(cpu, apicid); +} + +static __init void cpu_set_boot_apic(void) +{ + cpuid_to_apicid[0] =3D boot_cpu_physical_apicid; + cpu_update_apic(0, boot_cpu_physical_apicid, boot_cpu_apic_version); +} + +int generic_processor_info(int apicid, int version) +{ + int cpu, max =3D nr_cpu_ids; + + /* The boot CPU must be set before MADT/MPTABLE parsing happens */ + if (cpuid_to_apicid[0] =3D=3D BAD_APICID) + panic("Boot CPU APIC not registered yet\n"); + + if (apicid =3D=3D boot_cpu_physical_apicid) + return 0; + + if (disabled_cpu_apicid =3D=3D apicid) { + int thiscpu =3D num_processors + disabled_cpus; + + pr_warn("APIC: Disabling requested cpu. Processor %d/0x%x ignored.\n", + thiscpu, apicid); =20 + disabled_cpus++; + return -ENODEV; + } + + if (num_processors >=3D nr_cpu_ids) { + int thiscpu =3D max + disabled_cpus; + + pr_warn("APIC: NR_CPUS/possible_cpus limit of %i reached. " + "Processor %d/0x%x ignored.\n", max, thiscpu, apicid); + + disabled_cpus++; + return -EINVAL; + } + + cpu =3D allocate_logical_cpuid(apicid); + if (cpu < 0) { + disabled_cpus++; + return -EINVAL; + } + + cpu_update_apic(cpu, apicid, version); return cpu; } =20 + void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg, bool dmar) {