From nobody Thu Sep 11 21:09:01 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE26CC001B0 for ; Tue, 8 Aug 2023 16:35:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232520AbjHHQfL (ORCPT ); Tue, 8 Aug 2023 12:35:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48062 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233005AbjHHQeM (ORCPT ); Tue, 8 Aug 2023 12:34:12 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 385A31FF3; Tue, 8 Aug 2023 08:52:27 -0700 (PDT) Date: Tue, 08 Aug 2023 08:44:03 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691484243; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7OnvnQWhupjYWp1MgPVjQQ6/qDtRRqdDMe5rBy72aN4=; b=0xY+wkB+l1TsMEqOGglt+78JfbRTVXLbwhNiwk3q/6Y0M+F4ZaQFY0naFco1vxAct8S7do b0LFN+dDNbtB6RSQpjos3jKmZLTmZ3DjM/d/O+7lPiX3OwlMgUN9E7MD3L59mYLUCgnhEB CVuxatRsfxcwW5zB5dUhoAAsISjplUcl06q7zO+Z3xfaiHXi79h12vvqfZTqkQ5CJLN5T9 2MHzosC7NrmOzDk4w/R0bHM0/pg+6gK4OUyCJllJRO+1bcKwFJwAj4/WLyup9Bcsgs73nE C8NreI0kN0Vp6vWRBiU47wsn+acLwbLNiu0s3Y7O0X5wIRVGD8aOSq2SFwFVBg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691484243; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7OnvnQWhupjYWp1MgPVjQQ6/qDtRRqdDMe5rBy72aN4=; b=R0ip1rYHBfUYESlOctpK4iXatQW0xgbvJvVDPttr84ctu4GeEqC6WY8Daordl4hvRQqea0 K59lzXW+hXORtVDA== From: "tip-bot2 for Ard Biesheuvel" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/boot] x86/decompressor: Use standard calling convention for trampoline Cc: Ard Biesheuvel , "Borislav Petkov (AMD)" , "Kirill A. Shutemov" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20230807162720.545787-11-ardb@kernel.org> References: <20230807162720.545787-11-ardb@kernel.org> MIME-Version: 1.0 Message-ID: <169148424322.27769.15495483249376498258.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the x86/boot branch of tip: Commit-ID: 918a7a04e71745e99a0efc6753e587439b794b29 Gitweb: https://git.kernel.org/tip/918a7a04e71745e99a0efc6753e587439= b794b29 Author: Ard Biesheuvel AuthorDate: Mon, 07 Aug 2023 18:27:07 +02:00 Committer: Borislav Petkov (AMD) CommitterDate: Mon, 07 Aug 2023 20:43:59 +02:00 x86/decompressor: Use standard calling convention for trampoline Update the trampoline code so its arguments are passed via RDI and RSI, which matches the ordinary SysV calling convention for x86_64. This will allow this code to be called directly from C. Signed-off-by: Ard Biesheuvel Signed-off-by: Borislav Petkov (AMD) Acked-by: Kirill A. Shutemov Link: https://lore.kernel.org/r/20230807162720.545787-11-ardb@kernel.org --- arch/x86/boot/compressed/head_64.S | 27 +++++++++++++-------------- arch/x86/boot/compressed/pgtable.h | 2 +- 2 files changed, 14 insertions(+), 15 deletions(-) diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/= head_64.S index 91b5eee..c475042 100644 --- a/arch/x86/boot/compressed/head_64.S +++ b/arch/x86/boot/compressed/head_64.S @@ -444,9 +444,9 @@ SYM_CODE_START(startup_64) movq %r15, %rdi call paging_prepare =20 - /* Save the trampoline address in RCX */ - movq %rax, %rcx - + /* Pass the trampoline address and boolean flag as args #1 and #2 */ + movq %rax, %rdi + movq %rdx, %rsi leaq TRAMPOLINE_32BIT_CODE_OFFSET(%rax), %rax call *%rax =20 @@ -531,11 +531,14 @@ SYM_FUNC_START_LOCAL_NOALIGN(.Lrelocated) SYM_FUNC_END(.Lrelocated) =20 /* - * This is the 32-bit trampoline that will be copied over to low memory. + * This is the 32-bit trampoline that will be copied over to low memory. It + * will be called using the ordinary 64-bit calling convention from code + * running in 64-bit mode. * * Return address is at the top of the stack (might be above 4G). - * ECX contains the base address of the trampoline memory. - * Non zero RDX means trampoline needs to enable 5-level paging. + * The first argument (EDI) contains the 32-bit addressable base of the + * trampoline memory. A non-zero second argument (ESI) means that the + * trampoline needs to enable 5-level paging. */ SYM_CODE_START(trampoline_32bit_src) /* @@ -582,7 +585,7 @@ SYM_CODE_START(trampoline_32bit_src) movl %eax, %cr0 =20 /* Check what paging mode we want to be in after the trampoline */ - testl %edx, %edx + testl %esi, %esi jz 1f =20 /* We want 5-level paging: don't touch CR3 if it already points to 5-leve= l page tables */ @@ -597,21 +600,17 @@ SYM_CODE_START(trampoline_32bit_src) jz 3f 2: /* Point CR3 to the trampoline's new top level page table */ - leal TRAMPOLINE_32BIT_PGTABLE_OFFSET(%ecx), %eax + leal TRAMPOLINE_32BIT_PGTABLE_OFFSET(%edi), %eax movl %eax, %cr3 3: /* Set EFER.LME=3D1 as a precaution in case hypervsior pulls the rug */ - pushl %ecx - pushl %edx movl $MSR_EFER, %ecx rdmsr btsl $_EFER_LME, %eax /* Avoid writing EFER if no change was made (for TDX guest) */ jc 1f wrmsr -1: popl %edx - popl %ecx - +1: #ifdef CONFIG_X86_MCE /* * Preserve CR4.MCE if the kernel will enable #MC support. @@ -628,7 +627,7 @@ SYM_CODE_START(trampoline_32bit_src) =20 /* Enable PAE and LA57 (if required) paging modes */ orl $X86_CR4_PAE, %eax - testl %edx, %edx + testl %esi, %esi jz 1f orl $X86_CR4_LA57, %eax 1: diff --git a/arch/x86/boot/compressed/pgtable.h b/arch/x86/boot/compressed/= pgtable.h index 91dbb99..4e8cef1 100644 --- a/arch/x86/boot/compressed/pgtable.h +++ b/arch/x86/boot/compressed/pgtable.h @@ -14,7 +14,7 @@ =20 extern unsigned long *trampoline_32bit; =20 -extern void trampoline_32bit_src(void *return_ptr); +extern void trampoline_32bit_src(void *trampoline, bool enable_5lvl); =20 #endif /* __ASSEMBLER__ */ #endif /* BOOT_COMPRESSED_PAGETABLE_H */