From nobody Sun Feb 8 12:52:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77D34C001DF for ; Wed, 2 Aug 2023 22:20:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229610AbjHBWT5 (ORCPT ); Wed, 2 Aug 2023 18:19:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60250 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232408AbjHBWTe (ORCPT ); Wed, 2 Aug 2023 18:19:34 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2FE342733; Wed, 2 Aug 2023 15:19:31 -0700 (PDT) Date: Wed, 02 Aug 2023 22:19:27 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691014768; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=U5TI9eUVhciyNUwXUGgT/NKDN7f0lb+8FLyXuruuTvI=; b=SU7Gn2+RaxMBF81Nfm0LfZWkwJdYpNhFtISuKHh6W0AoweSRIxTiAagQDdQaE68tMW0s0q QjYnLTv11xCEgLSJIzv0oq0FHmqi9+GOv3TaaBuAW7fvXkT8dimAojhSCi09oKO+jcFqaI 36ObP+kVuutBrvWe4/TCqCqdT1K/cnPf2zifDscfTzFt2o+8gtJ1BTuyTrgR/sRYmdwo9z d/b/hFOgidBZ6Knvh+IkKQb5BUwLbD9P5DAqno4J1PhZuwTiWv6R1G+4b1F3nSUZRMGPa1 hTLAXg9yanCzJhnMks4qdtdJauGsk6QcaI5nCLOTJTsYxNP6cFptxb3gu23arw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691014768; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=U5TI9eUVhciyNUwXUGgT/NKDN7f0lb+8FLyXuruuTvI=; b=BNOVvP79PGs36hHhViUWWE78ouXpzZUHt3nQKMs8nprpqxRkXNYS0veZqQXzYu8lqaqOye ljPVo/dFnUT7ikAg== From: "tip-bot2 for Rick Edgecombe" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/shstk] x86/cpufeatures: Enable CET CR4 bit for shadow stack Cc: "Yu-cheng Yu" , Rick Edgecombe , Dave Hansen , "Borislav Petkov (AMD)" , Kees Cook , "Mike Rapoport (IBM)" , Pengfei Xu , John Allen , x86@kernel.org, linux-kernel@vger.kernel.org MIME-Version: 1.0 Message-ID: <169101476797.28540.9568036632645118391.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the x86/shstk branch of tip: Commit-ID: 0dc2a76092d9d513f5ea5eb3992d1459a67a3e7a Gitweb: https://git.kernel.org/tip/0dc2a76092d9d513f5ea5eb3992d1459a= 67a3e7a Author: Rick Edgecombe AuthorDate: Mon, 12 Jun 2023 17:11:04 -07:00 Committer: Dave Hansen CommitterDate: Wed, 02 Aug 2023 15:01:51 -07:00 x86/cpufeatures: Enable CET CR4 bit for shadow stack Setting CR4.CET is a prerequisite for utilizing any CET features, most of which also require setting MSRs. Kernel IBT already enables the CET CR4 bit when it detects IBT HW support and is configured with kernel IBT. However, future patches that enable userspace shadow stack support will need the bit set as well. So change the logic to enable it in either case. Clear MSR_IA32_U_CET in cet_disable() so that it can't live to see userspace in a new kexec-ed kernel that has CR4.CET set from kernel IBT. Co-developed-by: Yu-cheng Yu Signed-off-by: Yu-cheng Yu Signed-off-by: Rick Edgecombe Signed-off-by: Dave Hansen Reviewed-by: Borislav Petkov (AMD) Reviewed-by: Kees Cook Acked-by: Mike Rapoport (IBM) Tested-by: Pengfei Xu Tested-by: John Allen Tested-by: Kees Cook Link: https://lore.kernel.org/all/20230613001108.3040476-39-rick.p.edgecomb= e%40intel.com --- arch/x86/kernel/cpu/common.c | 35 +++++++++++++++++++++++++++-------- 1 file changed, 27 insertions(+), 8 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 52683fd..cf5275a 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -588,27 +588,43 @@ __noendbr void ibt_restore(u64 save) =20 static __always_inline void setup_cet(struct cpuinfo_x86 *c) { - u64 msr =3D CET_ENDBR_EN; + bool user_shstk, kernel_ibt; =20 - if (!HAS_KERNEL_IBT || - !cpu_feature_enabled(X86_FEATURE_IBT)) + if (!IS_ENABLED(CONFIG_X86_CET)) return; =20 - wrmsrl(MSR_IA32_S_CET, msr); + kernel_ibt =3D HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT); + user_shstk =3D cpu_feature_enabled(X86_FEATURE_SHSTK) && + IS_ENABLED(CONFIG_X86_USER_SHADOW_STACK); + + if (!kernel_ibt && !user_shstk) + return; + + if (user_shstk) + set_cpu_cap(c, X86_FEATURE_USER_SHSTK); + + if (kernel_ibt) + wrmsrl(MSR_IA32_S_CET, CET_ENDBR_EN); + else + wrmsrl(MSR_IA32_S_CET, 0); + cr4_set_bits(X86_CR4_CET); =20 - if (!ibt_selftest()) { + if (kernel_ibt && !ibt_selftest()) { pr_err("IBT selftest: Failed!\n"); wrmsrl(MSR_IA32_S_CET, 0); setup_clear_cpu_cap(X86_FEATURE_IBT); - return; } } =20 __noendbr void cet_disable(void) { - if (cpu_feature_enabled(X86_FEATURE_IBT)) - wrmsrl(MSR_IA32_S_CET, 0); + if (!(cpu_feature_enabled(X86_FEATURE_IBT) || + cpu_feature_enabled(X86_FEATURE_SHSTK))) + return; + + wrmsrl(MSR_IA32_S_CET, 0); + wrmsrl(MSR_IA32_U_CET, 0); } =20 /* @@ -1470,6 +1486,9 @@ static void __init cpu_parse_early_param(void) if (cmdline_find_option_bool(boot_command_line, "noxsaves")) setup_clear_cpu_cap(X86_FEATURE_XSAVES); =20 + if (cmdline_find_option_bool(boot_command_line, "nousershstk")) + setup_clear_cpu_cap(X86_FEATURE_USER_SHSTK); + arglen =3D cmdline_find_option(boot_command_line, "clearcpuid", arg, size= of(arg)); if (arglen <=3D 0) return;