From nobody Sun Feb 8 16:06:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 248E2C001B0 for ; Wed, 19 Jul 2023 22:49:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231379AbjGSWtb (ORCPT ); Wed, 19 Jul 2023 18:49:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42944 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231245AbjGSWrz (ORCPT ); Wed, 19 Jul 2023 18:47:55 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0C40726BA; Wed, 19 Jul 2023 15:47:41 -0700 (PDT) Date: Wed, 19 Jul 2023 22:47:39 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689806860; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=bG1OAkOfL55DIvNEq2Rs1D1O2SQlcTgoWxtBtLu+JOs=; b=WmwHJE7+Gfor0p0rZj8dx0NQqahxZ+1ekz+KD/P1RThNrgv+iyVmrFG7kJC0t9EBoS9mxu Zb/lPTEAlqL3aAOhYRuj6FX5+rACsFbb2domqlPMjiC7Vz9hkPa5Ui/Lpope6afST/Lww8 i8glKuNEUEb92Z3w/yuIImUcGDUITHSVdlFz0mvdBHg72KxuzZZcX4usCfnRzcireBqOHp U3GPg+Je1nEWulPiizrzx2pvBPetm3nWwBds0mZr2FXNWCHUmTI/g/ukMhuhbgBqasQsjI h0tGoKlAQ1NpEhocottbgIodxOLlpOQr2W3gMUaOaqmfHv+7FWnBSsr8dBTMWg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689806860; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=bG1OAkOfL55DIvNEq2Rs1D1O2SQlcTgoWxtBtLu+JOs=; b=zDiyzdAlZCWMlhj7bKxSn8FHj1tx8lGS2Jwo/FChojfAK76cuyx3jLVF/itJZIiOhLZTCv RmOZc9aVwWIA81Aw== From: "tip-bot2 for Rick Edgecombe" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/shstk] x86/mm: Update ptep/pmdp_set_wrprotect() for _PAGE_SAVED_DIRTY Cc: "Yu-cheng Yu" , Rick Edgecombe , Dave Hansen , "Mike Rapoport (IBM)" , Pengfei Xu , John Allen , Kees Cook , x86@kernel.org, linux-kernel@vger.kernel.org MIME-Version: 1.0 Message-ID: <168980685940.28540.1641055647652693070.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the x86/shstk branch of tip: Commit-ID: 1f6f66f62e8cba909abc4fb59de3b57d8c5a9783 Gitweb: https://git.kernel.org/tip/1f6f66f62e8cba909abc4fb59de3b57d8= c5a9783 Author: Rick Edgecombe AuthorDate: Mon, 12 Jun 2023 17:10:37 -07:00 Committer: Rick Edgecombe CommitterDate: Tue, 11 Jul 2023 14:12:19 -07:00 x86/mm: Update ptep/pmdp_set_wrprotect() for _PAGE_SAVED_DIRTY When shadow stack is in use, Write=3D0,Dirty=3D1 PTE are preserved for shadow stack. Copy-on-write PTEs then have Write=3D0,SavedDirty=3D1. When a PTE goes from Write=3D1,Dirty=3D1 to Write=3D0,SavedDirty=3D1, it co= uld become a transient shadow stack PTE in two cases: 1. Some processors can start a write but end up seeing a Write=3D0 PTE by the time they get to the Dirty bit, creating a transient shadow stack PTE. However, this will not occur on processors supporting shadow stack, and a TLB flush is not necessary. 2. When _PAGE_DIRTY is replaced with _PAGE_SAVED_DIRTY non-atomically, a transient shadow stack PTE can be created as a result. Prevent the second case when doing a write protection and Dirty->SavedDirty shift at the same time with a CMPXCHG loop. The first case Note, in the PAE case CMPXCHG will need to operate on 8 byte, but try_cmpxchg() will not use CMPXCHG8B, so it cannot operate on a full PAE PTE. However the exiting logic is not operating on a full 8 byte region either, and relies on the fact that the Write bit is in the first 4 bytes when doing the clear_bit(). Since both the Dirty, SavedDirty and Write bits are in the first 4 bytes, casting to a long will be similar to the existing behavior which also casts to a long. Dave Hansen, Jann Horn, Andy Lutomirski, and Peter Zijlstra provided many insights to the issue. Jann Horn provided the CMPXCHG solution. Co-developed-by: Yu-cheng Yu Signed-off-by: Yu-cheng Yu Signed-off-by: Rick Edgecombe Signed-off-by: Dave Hansen Acked-by: Mike Rapoport (IBM) Tested-by: Pengfei Xu Tested-by: John Allen Tested-by: Kees Cook Link: https://lore.kernel.org/all/20230613001108.3040476-12-rick.p.edgecomb= e%40intel.com --- arch/x86/include/asm/pgtable.h | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h index 0c0747c..b48d07a 100644 --- a/arch/x86/include/asm/pgtable.h +++ b/arch/x86/include/asm/pgtable.h @@ -1190,7 +1190,17 @@ static inline pte_t ptep_get_and_clear_full(struct m= m_struct *mm, static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep) { - clear_bit(_PAGE_BIT_RW, (unsigned long *)&ptep->pte); + /* + * Avoid accidentally creating shadow stack PTEs + * (Write=3D0,Dirty=3D1). Use cmpxchg() to prevent races with + * the hardware setting Dirty=3D1. + */ + pte_t old_pte, new_pte; + + old_pte =3D READ_ONCE(*ptep); + do { + new_pte =3D pte_wrprotect(old_pte); + } while (!try_cmpxchg((long *)&ptep->pte, (long *)&old_pte, *(long *)&new= _pte)); } =20 #define flush_tlb_fix_spurious_fault(vma, address, ptep) do { } while (0) @@ -1242,7 +1252,17 @@ static inline pud_t pudp_huge_get_and_clear(struct m= m_struct *mm, static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp) { - clear_bit(_PAGE_BIT_RW, (unsigned long *)pmdp); + /* + * Avoid accidentally creating shadow stack PTEs + * (Write=3D0,Dirty=3D1). Use cmpxchg() to prevent races with + * the hardware setting Dirty=3D1. + */ + pmd_t old_pmd, new_pmd; + + old_pmd =3D READ_ONCE(*pmdp); + do { + new_pmd =3D pmd_wrprotect(old_pmd); + } while (!try_cmpxchg((long *)pmdp, (long *)&old_pmd, *(long *)&new_pmd)); } =20 #ifndef pmdp_establish