From nobody Tue Sep 9 07:32:55 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6E6FEB64DA for ; Wed, 19 Jul 2023 07:21:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230218AbjGSHVZ (ORCPT ); Wed, 19 Jul 2023 03:21:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52880 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229987AbjGSHVA (ORCPT ); Wed, 19 Jul 2023 03:21:00 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E030B210B; Wed, 19 Jul 2023 00:20:43 -0700 (PDT) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36J7G9oC032355; Wed, 19 Jul 2023 07:20:25 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=X8U7m6oeXAUjm/N5kYm0WAl5wvbpfFgciZSimFM50A8=; b=G0dEsCpqrJY9vH8e3Kil2NAt8GTB9Boy2ZCQP2GyJ0IA8KGMlvYwJWhAsqxcG/M1oKPt c1DFSDgCeIr2BJG18MCSxkP1yhpCsHQf4PV5GfmLfqd+bTVghtgtXAMY2TIWOWfhUrip NThmO3sLfZ9EMnljsSKTtvIJm22p+3dczhmGdulSA+/Spd3VAfse4P2L3vgAJ7l7EsGl SOnpIXJv1qPYSiNKAhHKUjh+aqOcIZAda4fQr/tJ3BAo2x4aKfHtopvVHEkJJsLOE3wm Xpt7sV1jqScnVZQF4jmo/zNEtQFiE4V+0in3Y2ItVOANs6LxYznEK9FMW7NQUdmnrUa9 Ow== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rx8sk087t-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Jul 2023 07:20:24 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 36J7KKSo022626; Wed, 19 Jul 2023 07:20:20 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3rumhm1v72-1; Wed, 19 Jul 2023 07:20:20 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 36J7KKI9022612; Wed, 19 Jul 2023 07:20:20 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-krichai-hyd.qualcomm.com [10.213.110.112]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 36J7KKre022582; Wed, 19 Jul 2023 07:20:20 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 4058933) id D5D014B07; Wed, 19 Jul 2023 12:50:19 +0530 (+0530) From: Krishna chaitanya chundru To: manivannan.sadhasivam@linaro.org Cc: helgaas@kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, quic_vbadigan@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, krzysztof.kozlowski@linaro.org, Krishna chaitanya chundru , Manivannan Sadhasivam , Andy Gross , Bjorn Andersson , Konrad Dybcio , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS) Subject: [PATCH v10 1/4] dt-bindings: PCI: qcom: ep: Add interconnects path Date: Wed, 19 Jul 2023 12:50:15 +0530 Message-Id: <1689751218-24492-2-git-send-email-quic_krichai@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1689751218-24492-1-git-send-email-quic_krichai@quicinc.com> References: <1689751218-24492-1-git-send-email-quic_krichai@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: j5RE-AyD1ly7aUPmN4MrNP51q2U9nhI_ X-Proofpoint-ORIG-GUID: j5RE-AyD1ly7aUPmN4MrNP51q2U9nhI_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-19_04,2023-07-18_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 malwarescore=0 bulkscore=0 phishscore=0 mlxlogscore=999 impostorscore=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 priorityscore=1501 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307190066 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Some platforms may not boot if a device driver doesn't initialize the interconnect path. Mostly it is handled by the bootloader but we have starting to see cases where bootloader simply ignores them. Add the "pcie-mem" & "cpu-pcie" interconnect path as a required property to the bindings. Signed-off-by: Krishna chaitanya chundru Acked-by: Manivannan Sadhasivam Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 15 +++++++++++++= ++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Docu= mentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index 8111122..e553341 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -71,6 +71,14 @@ properties: description: GPIO used as WAKE# output signal maxItems: 1 =20 + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: pcie-mem + - const: cpu-pcie + resets: maxItems: 1 =20 @@ -98,6 +106,8 @@ required: - interrupts - interrupt-names - reset-gpios + - interconnects + - interconnect-names - resets - reset-names - power-domains @@ -167,7 +177,9 @@ examples: - | #include #include + #include #include + pcie_ep: pcie-ep@1c00000 { compatible =3D "qcom,sdx55-pcie-ep"; reg =3D <0x01c00000 0x3000>, @@ -194,6 +206,9 @@ examples: interrupts =3D , ; interrupt-names =3D "global", "doorbell"; + interconnects =3D <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>, + <&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_PCIE_0= >; + interconnect-names =3D "pcie-mem", "cpu-pcie"; reset-gpios =3D <&tlmm 57 GPIO_ACTIVE_LOW>; wake-gpios =3D <&tlmm 53 GPIO_ACTIVE_LOW>; resets =3D <&gcc GCC_PCIE_BCR>; --=20 2.7.4 From nobody Tue Sep 9 07:32:55 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 791EAC001DE for ; Wed, 19 Jul 2023 07:21:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230150AbjGSHVO (ORCPT ); Wed, 19 Jul 2023 03:21:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52786 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229785AbjGSHUy (ORCPT ); Wed, 19 Jul 2023 03:20:54 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58B521BE3; Wed, 19 Jul 2023 00:20:38 -0700 (PDT) Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36J6KDFR023945; Wed, 19 Jul 2023 07:20:24 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=44cme+QGmmueWM5NMsqd3ar9uFIUlwYHxlf35NJHfRc=; b=gYZmGzO1uJeWnTVqEzbURLvressXyJzOWx11gffGCWG7P7TP/8nRJ9szuwde8MyY3exa eWfp0ScUAug0c59faxgjfSO0unkIvkm3/kt7CELmCu+pLlo/vHp/2RCE0WBHrkMLf9LX xl5Kw5pnlzTMymg6seGFDGmlCLiA/KOX6O50dDp3o7tn+qMO2mZSUV4ifgwmDhs7I56F VDnKJkoKlW1LnxGVR1OixziiXTZlTpa8kqniU48wzCNMf/0M+UqxmbIIWmMJwwIvVXE2 TyeCJ2rwUQ7NIwFPhxOOYVAtZ73sALD7N6meJ7/VYc7q6AEVDsUTimXMrsyZCVuxy2s8 Lg== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rx7410ev7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Jul 2023 07:20:24 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 36J7KLiV022655; Wed, 19 Jul 2023 07:20:21 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3rumhm1v78-1; Wed, 19 Jul 2023 07:20:21 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 36J7KKXI022632; Wed, 19 Jul 2023 07:20:21 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-krichai-hyd.qualcomm.com [10.213.110.112]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 36J7KKnU022618; Wed, 19 Jul 2023 07:20:20 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 4058933) id 126244B0A; Wed, 19 Jul 2023 12:50:20 +0530 (+0530) From: Krishna chaitanya chundru To: manivannan.sadhasivam@linaro.org Cc: helgaas@kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, quic_vbadigan@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, krzysztof.kozlowski@linaro.org, Krishna chaitanya chundru , Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS) Subject: [PATCH v10 2/4] arm: dts: qcom: sdx65: Add PCIe EP interconnect path Date: Wed, 19 Jul 2023 12:50:16 +0530 Message-Id: <1689751218-24492-3-git-send-email-quic_krichai@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1689751218-24492-1-git-send-email-quic_krichai@quicinc.com> References: <1689751218-24492-1-git-send-email-quic_krichai@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: xRkYrMUJhXv7dZpmi_v6Dp2S7zvgYDkr X-Proofpoint-ORIG-GUID: xRkYrMUJhXv7dZpmi_v6Dp2S7zvgYDkr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-19_04,2023-07-18_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 impostorscore=0 bulkscore=0 suspectscore=0 spamscore=0 priorityscore=1501 mlxlogscore=869 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307190066 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add pcie-mem & cpu-pcie interconnect path ifor PCIe EP to sdx65 platform. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Krishna chaitanya chundru --- arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qco= m/qcom-sdx65.dtsi index 1a35830..69fe7e5 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi @@ -332,6 +332,10 @@ ; interrupt-names =3D "global", "doorbell"; =20 + interconnects =3D <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>, + <&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_PCIE_0>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + resets =3D <&gcc GCC_PCIE_BCR>; reset-names =3D "core"; =20 --=20 2.7.4 From nobody Tue Sep 9 07:32:55 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2713EEB64DA for ; Wed, 19 Jul 2023 07:21:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229477AbjGSHVS (ORCPT ); Wed, 19 Jul 2023 03:21:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230049AbjGSHUy (ORCPT ); Wed, 19 Jul 2023 03:20:54 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB2051FE8; Wed, 19 Jul 2023 00:20:38 -0700 (PDT) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36J7477V011074; Wed, 19 Jul 2023 07:20:24 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=9o7YPoNhptdVPiBy2o7oEDnBNhfZkA/Z5kBzrOCyRO4=; b=WwoeuLtt7QeD8UC80QWlPUj3YdNrDE2MG5w3f+ONt/M76VUlVjr702b4EEd+Vs5uJzXm 9oyv0JilkHiJakabA8i691jOZ1zhaCBIqc2j2cS69fyjaGTbgwWzTSEp1BL9SxVTN5Iz K+2I6MmVlK5TkLHXZ8mv8hewmz3x7rUT1C43ApprIZuxR33fvHYtmYBLsTn776t0vzlb d1PC/ED1rLDEUihMkcq0wBf/Md+KMWFE5+Na/b2vseM8/aVFz8VpryAdVMrrKb0fG/hA lY6An0j3HCtM9IrdNjPLifvgCZaZUc7k1+hwLDkW9TC1Vm4A7MVN3YZrpZUmpt4kHgno Rg== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rwn90asa6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Jul 2023 07:20:24 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 36J7KLr2022656; Wed, 19 Jul 2023 07:20:21 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3rumhm1v77-1; Wed, 19 Jul 2023 07:20:21 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 36J7KKor022629; Wed, 19 Jul 2023 07:20:21 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-krichai-hyd.qualcomm.com [10.213.110.112]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 36J7KKpN022619; Wed, 19 Jul 2023 07:20:20 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 4058933) id 4468A4B0E; Wed, 19 Jul 2023 12:50:20 +0530 (+0530) From: Krishna chaitanya chundru To: manivannan.sadhasivam@linaro.org Cc: helgaas@kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, quic_vbadigan@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, krzysztof.kozlowski@linaro.org, Krishna chaitanya chundru , Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS) Subject: [PATCH v10 3/4] arm: dts: qcom: sdx55: Add CPU PCIe EP interconnect path Date: Wed, 19 Jul 2023 12:50:17 +0530 Message-Id: <1689751218-24492-4-git-send-email-quic_krichai@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1689751218-24492-1-git-send-email-quic_krichai@quicinc.com> References: <1689751218-24492-1-git-send-email-quic_krichai@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: V2Z42PCaNRR-f_ZsEK6VmEHnQy6f8Js8 X-Proofpoint-ORIG-GUID: V2Z42PCaNRR-f_ZsEK6VmEHnQy6f8Js8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-19_04,2023-07-18_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 bulkscore=0 phishscore=0 spamscore=0 adultscore=0 mlxlogscore=801 lowpriorityscore=0 mlxscore=0 suspectscore=0 impostorscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307190066 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add cpu-pcie interconnect path for PCIe EP to sdx55 platform. Signed-off-by: Krishna chaitanya chundru Reviewed-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qco= m/qcom-sdx55.dtsi index df3cd9c..a7c0c26 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -422,8 +422,9 @@ interrupt-names =3D "global", "doorbell"; =20 - interconnects =3D <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>; - interconnect-names =3D "pcie-mem"; + interconnects =3D <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>, + <&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_PCIE_0>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; =20 resets =3D <&gcc GCC_PCIE_BCR>; reset-names =3D "core"; --=20 2.7.4 From nobody Tue Sep 9 07:32:55 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68900EB64DA for ; Wed, 19 Jul 2023 07:21:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230049AbjGSHVV (ORCPT ); Wed, 19 Jul 2023 03:21:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52832 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230079AbjGSHU4 (ORCPT ); Wed, 19 Jul 2023 03:20:56 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A4152106; Wed, 19 Jul 2023 00:20:41 -0700 (PDT) Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36J5kEu9018635; Wed, 19 Jul 2023 07:20:25 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=fxbSAOTbCRZKV5fgWQzs58YIFmsL+43nXlNRoGtbXoM=; b=PI2EBp703wb/eE4xETJOqYpdow9AcjUe7c+WP4XIquTLyl/Ij0oANXQgQjE8tf+TQowa CLTpeisXNsQdd0PocPL9nrUCp46Vy3Ko1b7pIfZNF8Be9znG92ZxV69lBtSElAS2c2NJ vrZQD0oHBKEcAirqb36BlY4Blxs+1b2JZfqRbQnO58gGoahS8m70eqW2/GyLDLHkz43O //UdVJY2rGIM5CFYynVn4YZ7zk+Xe2XFjkRUioH1Y0f7LZpWw3zE7EKUdwa1ulQ1XZ4t j12Ev/KG8R2zwkaJDOPTNahTdgMstAe8l6KtW/weqtWnYxaHSsBqMyGHL7boZy1Tg+fh hw== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rx7410ev6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Jul 2023 07:20:24 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 36J7EfA8017367; Wed, 19 Jul 2023 07:20:21 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3rumhm1v7n-1; Wed, 19 Jul 2023 07:20:21 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 36J7KLvc022672; Wed, 19 Jul 2023 07:20:21 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-krichai-hyd.qualcomm.com [10.213.110.112]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 36J7KLlD022642; Wed, 19 Jul 2023 07:20:21 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 4058933) id 7C97C4B11; Wed, 19 Jul 2023 12:50:20 +0530 (+0530) From: Krishna chaitanya chundru To: manivannan.sadhasivam@linaro.org Cc: helgaas@kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, quic_vbadigan@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, krzysztof.kozlowski@linaro.org, Krishna chaitanya chundru , Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas Subject: [PATCH v10 4/4] PCI: qcom-ep: Add ICC bandwidth voting support Date: Wed, 19 Jul 2023 12:50:18 +0530 Message-Id: <1689751218-24492-5-git-send-email-quic_krichai@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1689751218-24492-1-git-send-email-quic_krichai@quicinc.com> References: <1689751218-24492-1-git-send-email-quic_krichai@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ermn3eukH_aiafSZPORWICjnzMeyWXSr X-Proofpoint-ORIG-GUID: ermn3eukH_aiafSZPORWICjnzMeyWXSr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-19_04,2023-07-18_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 impostorscore=0 bulkscore=0 suspectscore=0 spamscore=0 priorityscore=1501 mlxlogscore=999 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307190066 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for voting interconnect (ICC) bandwidth based on the link speed and width. This commit is inspired from the basic interconnect support added to pcie-qcom driver in commit c4860af88d0c ("PCI: qcom: Add basic interconnect support"). The interconnect support is kept optional to be backward compatible with legacy devicetrees. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 71 +++++++++++++++++++++++++++= ++++ 1 file changed, 71 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/contro= ller/dwc/pcie-qcom-ep.c index 0fe7f06..7460b3f 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -133,6 +134,11 @@ #define CORE_RESET_TIME_US_MAX 1005 #define WAKE_DELAY_US 2000 /* 2 ms */ =20 +#define PCIE_GEN1_BW_MBPS 250 +#define PCIE_GEN2_BW_MBPS 500 +#define PCIE_GEN3_BW_MBPS 985 +#define PCIE_GEN4_BW_MBPS 1969 + #define to_pcie_ep(x) dev_get_drvdata((x)->dev) =20 enum qcom_pcie_ep_link_status { @@ -178,6 +184,8 @@ struct qcom_pcie_ep { struct phy *phy; struct dentry *debugfs; =20 + struct icc_path *icc_mem; + struct clk_bulk_data *clks; int num_clks; =20 @@ -253,8 +261,49 @@ static void qcom_pcie_dw_stop_link(struct dw_pcie *pci) disable_irq(pcie_ep->perst_irq); } =20 +static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep) +{ + struct dw_pcie *pci =3D &pcie_ep->pci; + u32 offset, status, bw; + int speed, width; + int ret; + + if (!pcie_ep->icc_mem) + return; + + offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + status =3D readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); + + speed =3D FIELD_GET(PCI_EXP_LNKSTA_CLS, status); + width =3D FIELD_GET(PCI_EXP_LNKSTA_NLW, status); + + switch (speed) { + case 1: + bw =3D MBps_to_icc(PCIE_GEN1_BW_MBPS); + break; + case 2: + bw =3D MBps_to_icc(PCIE_GEN2_BW_MBPS); + break; + case 3: + bw =3D MBps_to_icc(PCIE_GEN3_BW_MBPS); + break; + default: + dev_warn(pci->dev, "using default GEN4 bandwidth\n"); + fallthrough; + case 4: + bw =3D MBps_to_icc(PCIE_GEN4_BW_MBPS); + break; + } + + ret =3D icc_set_bw(pcie_ep->icc_mem, 0, width * bw); + if (ret) + dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", + ret); +} + static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep) { + struct dw_pcie *pci =3D &pcie_ep->pci; int ret; =20 ret =3D clk_bulk_prepare_enable(pcie_ep->num_clks, pcie_ep->clks); @@ -277,8 +326,24 @@ static int qcom_pcie_enable_resources(struct qcom_pcie= _ep *pcie_ep) if (ret) goto err_phy_exit; =20 + /* + * Some Qualcomm platforms require interconnect bandwidth constraints + * to be set before enabling interconnect clocks. + * + * Set an initial peak bandwidth corresponding to single-lane Gen 1 + * for the pcie-mem path. + */ + ret =3D icc_set_bw(pcie_ep->icc_mem, 0, MBps_to_icc(PCIE_GEN1_BW_MBPS)); + if (ret) { + dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", + ret); + goto err_phy_off; + } + return 0; =20 +err_phy_off: + phy_power_off(pcie_ep->phy); err_phy_exit: phy_exit(pcie_ep->phy); err_disable_clk: @@ -289,6 +354,7 @@ static int qcom_pcie_enable_resources(struct qcom_pcie_= ep *pcie_ep) =20 static void qcom_pcie_disable_resources(struct qcom_pcie_ep *pcie_ep) { + icc_set_bw(pcie_ep->icc_mem, 0, 0); phy_power_off(pcie_ep->phy); phy_exit(pcie_ep->phy); clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks); @@ -550,6 +616,10 @@ static int qcom_pcie_ep_get_resources(struct platform_= device *pdev, if (IS_ERR(pcie_ep->phy)) ret =3D PTR_ERR(pcie_ep->phy); =20 + pcie_ep->icc_mem =3D devm_of_icc_get(dev, "pcie-mem"); + if (IS_ERR(pcie_ep->icc_mem)) + ret =3D PTR_ERR(pcie_ep->icc_mem); + return ret; } =20 @@ -573,6 +643,7 @@ static irqreturn_t qcom_pcie_ep_global_irq_thread(int i= rq, void *data) } else if (FIELD_GET(PARF_INT_ALL_BME, status)) { dev_dbg(dev, "Received BME event. Link is enabled!\n"); pcie_ep->link_status =3D QCOM_PCIE_EP_LINK_ENABLED; + qcom_pcie_ep_icc_update(pcie_ep); pci_epc_bme_notify(pci->ep.epc); } else if (FIELD_GET(PARF_INT_ALL_PM_TURNOFF, status)) { dev_dbg(dev, "Received PM Turn-off event! Entering L23\n"); --=20 2.7.4