From nobody Sun Feb 8 13:39:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4CFBEB64DA for ; Fri, 16 Jun 2023 19:19:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346161AbjFPTTH (ORCPT ); Fri, 16 Jun 2023 15:19:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48112 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346005AbjFPTRL (ORCPT ); Fri, 16 Jun 2023 15:17:11 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3573F35A7; Fri, 16 Jun 2023 12:17:05 -0700 (PDT) Date: Fri, 16 Jun 2023 19:17:03 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1686943023; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=BYKFeatUBoOPBvwxlIsSnk4Tb5+E9gS0xg4pcEolCM8=; b=s3zyMKQs5qadjoAxqNan5FqTshvHBULaLv1BvKrLCYWiEYSiD1wvLdl8lRvYVuI0I/TE9d o6CwInak3jw3rAcA0LCznFqR3q4TfLTY+RoWcbZXIon1AnPvocrWYeuYO8QPNH5H/nI+6L 1Sab8SVKOHo3hJfi367hrKDBEtVruAFCLNmDXmChjOp2ErrcKBWo9LzUGBc+KWqyISWBZy 6/8V6dKUHW4eiS8mumt11CbejYty19PfYroSLBuhJ9LsI4/MjRRDIYMBLP7xnzHV2YmtjC XdfhM9IqUc3Vn97Jx0vE6pI3aXGuEHZJ8wWfzhEO7pjCaCwJ68tM1HMlaHf/yQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1686943023; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=BYKFeatUBoOPBvwxlIsSnk4Tb5+E9gS0xg4pcEolCM8=; b=lzJpGUNQyzbZ6/cHLFrXn2+pzq3vHq7wgh8sduZt7KxquLNy6a0Nmh7gU5j01NgNuiDUzD Z5hWBBtyMHrLW3Cw== From: "tip-bot2 for Rick Edgecombe" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/shstk] x86/mm: Update ptep/pmdp_set_wrprotect() for _PAGE_SAVED_DIRTY Cc: "Yu-cheng Yu" , Rick Edgecombe , Dave Hansen , "Mike Rapoport (IBM)" , Pengfei Xu , John Allen , Kees Cook , x86@kernel.org, linux-kernel@vger.kernel.org MIME-Version: 1.0 Message-ID: <168694302336.404.16379064029653101571.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the x86/shstk branch of tip: Commit-ID: 75c1d1854306f4c978105bafe3ec1e030548cec5 Gitweb: https://git.kernel.org/tip/75c1d1854306f4c978105bafe3ec1e030= 548cec5 Author: Rick Edgecombe AuthorDate: Mon, 12 Jun 2023 17:10:37 -07:00 Committer: Dave Hansen CommitterDate: Thu, 15 Jun 2023 16:31:33 -07:00 x86/mm: Update ptep/pmdp_set_wrprotect() for _PAGE_SAVED_DIRTY When shadow stack is in use, Write=3D0,Dirty=3D1 PTE are preserved for shadow stack. Copy-on-write PTEs then have Write=3D0,SavedDirty=3D1. When a PTE goes from Write=3D1,Dirty=3D1 to Write=3D0,SavedDirty=3D1, it co= uld become a transient shadow stack PTE in two cases: 1. Some processors can start a write but end up seeing a Write=3D0 PTE by the time they get to the Dirty bit, creating a transient shadow stack PTE. However, this will not occur on processors supporting shadow stack, and a TLB flush is not necessary. 2. When _PAGE_DIRTY is replaced with _PAGE_SAVED_DIRTY non-atomically, a transient shadow stack PTE can be created as a result. Prevent the second case when doing a write protection and Dirty->SavedDirty shift at the same time with a CMPXCHG loop. The first case Note, in the PAE case CMPXCHG will need to operate on 8 byte, but try_cmpxchg() will not use CMPXCHG8B, so it cannot operate on a full PAE PTE. However the exiting logic is not operating on a full 8 byte region either, and relies on the fact that the Write bit is in the first 4 bytes when doing the clear_bit(). Since both the Dirty, SavedDirty and Write bits are in the first 4 bytes, casting to a long will be similar to the existing behavior which also casts to a long. Dave Hansen, Jann Horn, Andy Lutomirski, and Peter Zijlstra provided many insights to the issue. Jann Horn provided the CMPXCHG solution. Co-developed-by: Yu-cheng Yu Signed-off-by: Yu-cheng Yu Signed-off-by: Rick Edgecombe Signed-off-by: Dave Hansen Acked-by: Mike Rapoport (IBM) Tested-by: Pengfei Xu Tested-by: John Allen Tested-by: Kees Cook Link: https://lore.kernel.org/all/20230613001108.3040476-12-rick.p.edgecomb= e%40intel.com --- arch/x86/include/asm/pgtable.h | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h index a1883d8..13fdad2 100644 --- a/arch/x86/include/asm/pgtable.h +++ b/arch/x86/include/asm/pgtable.h @@ -1189,7 +1189,17 @@ static inline pte_t ptep_get_and_clear_full(struct m= m_struct *mm, static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep) { - clear_bit(_PAGE_BIT_RW, (unsigned long *)&ptep->pte); + /* + * Avoid accidentally creating shadow stack PTEs + * (Write=3D0,Dirty=3D1). Use cmpxchg() to prevent races with + * the hardware setting Dirty=3D1. + */ + pte_t old_pte, new_pte; + + old_pte =3D READ_ONCE(*ptep); + do { + new_pte =3D pte_wrprotect(old_pte); + } while (!try_cmpxchg((long *)&ptep->pte, (long *)&old_pte, *(long *)&new= _pte)); } =20 #define flush_tlb_fix_spurious_fault(vma, address, ptep) do { } while (0) @@ -1241,7 +1251,17 @@ static inline pud_t pudp_huge_get_and_clear(struct m= m_struct *mm, static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp) { - clear_bit(_PAGE_BIT_RW, (unsigned long *)pmdp); + /* + * Avoid accidentally creating shadow stack PTEs + * (Write=3D0,Dirty=3D1). Use cmpxchg() to prevent races with + * the hardware setting Dirty=3D1. + */ + pmd_t old_pmd, new_pmd; + + old_pmd =3D READ_ONCE(*pmdp); + do { + new_pmd =3D pmd_wrprotect(old_pmd); + } while (!try_cmpxchg((long *)pmdp, (long *)&old_pmd, *(long *)&new_pmd)); } =20 #ifndef pmdp_establish