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Thu, 8 Jun 2023 13:42:59 -0500 From: Manikanta Guntupalli To: , , , , , , , , , CC: , , Manikanta Guntupalli Subject: [PATCH V2] gpio: zynq: fix zynqmp_gpio not an immutable chip warning Date: Fri, 9 Jun 2023 00:12:52 +0530 Message-ID: <1686249772-26231-1-git-send-email-manikanta.guntupalli@amd.com> X-Mailer: git-send-email 2.1.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00026367:EE_|PH8PR12MB7230:EE_ X-MS-Office365-Filtering-Correlation-Id: 26cc4dba-785b-429f-b002-08db68503b8d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: dj+B5aJFXRNEYsnUIN/2b8Ijhehzr7Dr9jvHVS/m2N3FmywK56kCM1a19OLo+/9Ne2CV+SmoWQjFoVkQRLuHteEM2MWhhr96E8G9+iukklozHTav+BrrWWuvwGtOXBM40UXX1Tpw5h8XvTcJgL5vIa9ZuQrEN05cT7fAdqAmvisIK0i1QgRklbaQ4G5MKljBuTT1GpTlHNetuuD5cnG8OPryuMPAj0fEigLgCn9hRMo4O1gdeHEv/dBP64OJgo5xwldfSiYGEVFZeDnhAxINWun+mDhwgOyE4tI79HtX5530F2Wz0v01Y+cyZg/Wh4m2XDj+jg0IF16S1gURwrsqjZE6Hg5IrZ4DEs+joDUvQozwadWVjFDsMwtuPy2lPTusZy9lAk8W7VSk6VTe3ddpoX48xs9/7j9j61tukSp7ZXLWeRw8OlyzJpAqDfQDHJKeLKAIqLBCx7h5g7n3s86zWqYgn+nG/HBK54gzSZLdsgjUBjzPgf4G5Oq8lZEI46lmKm/h0dxXuqrCxxdVHrKxFJJ8d8T3hUMviGjQWEI9l0el3eV5Syimt4jGH0CLmFfUtYqIeyevFsnA61sSw/6uTcs/d0I7NqnCGdl/+6pl/3BES7lTi6aBR3AblvuEK5CbN/VQdwdEp6rYJ0g+P3h+ejNO76GEjnL4+SQrSBWwq4G1k4yLC1dvz1+SARd46hDdNEqhAuHqUkDchtmO7LlOc/WqWrgClUrDReVAVvAKMCuVXPsaUAdbw1GJ+aouVUCE4svExol8HHVlfmdRPQQQ/xkt2DRk36PZlWxkvqngK5csTgOkx/5hHFMPnNs5LdYxSpsAFxCz7GWO1QqqO/urTw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(376002)(136003)(396003)(39860400002)(346002)(451199021)(40470700004)(36840700001)(46966006)(82310400005)(41300700001)(26005)(40460700003)(86362001)(426003)(478600001)(70586007)(6666004)(54906003)(316002)(4326008)(110136005)(356005)(40480700001)(36756003)(186003)(70206006)(81166007)(2616005)(336012)(82740400003)(921005)(83380400001)(5660300002)(8936002)(8676002)(36860700001)(47076005)(44832011)(2906002)(36900700001)(2101003)(83996005);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jun 2023 18:43:20.8245 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 26cc4dba-785b-429f-b002-08db68503b8d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00026367.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7230 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Make the struct irq_chip const and flag it as IRQCHIP_IMMUTABLE, call gpiochip_disable_irq() in the .irq_mask() callback and gpiochip_enable_irq() in the .irq_unmask() callback to fix "gpio gpiochip1: (zynqmp_gpio): not an immutable chip" warning. Signed-off-by: Manikanta Guntupalli Reviewed-by: Linus Walleij --- Changes for V2: Add gpiochip_disable_irq() in the .irq_mask() callback and gpiochip_enable_irq() in the .irq_unmask() callback --- drivers/gpio/gpio-zynq.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/drivers/gpio/gpio-zynq.c b/drivers/gpio/gpio-zynq.c index 06c6401f02b8..c334e46033ba 100644 --- a/drivers/gpio/gpio-zynq.c +++ b/drivers/gpio/gpio-zynq.c @@ -151,8 +151,8 @@ struct zynq_platform_data { int bank_max[ZYNQMP_GPIO_MAX_BANK]; }; =20 -static struct irq_chip zynq_gpio_level_irqchip; -static struct irq_chip zynq_gpio_edge_irqchip; +static const struct irq_chip zynq_gpio_level_irqchip; +static const struct irq_chip zynq_gpio_edge_irqchip; =20 /** * zynq_gpio_is_zynq - test if HW is zynq or zynqmp @@ -404,9 +404,12 @@ static int zynq_gpio_get_direction(struct gpio_chip *c= hip, unsigned int pin) static void zynq_gpio_irq_mask(struct irq_data *irq_data) { unsigned int device_pin_num, bank_num, bank_pin_num; + const unsigned long offset =3D irqd_to_hwirq(irq_data); + struct gpio_chip *chip =3D irq_data_get_irq_chip_data(irq_data); struct zynq_gpio *gpio =3D gpiochip_get_data(irq_data_get_irq_chip_data(irq_data)); =20 + gpiochip_disable_irq(chip, offset); device_pin_num =3D irq_data->hwirq; zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); writel_relaxed(BIT(bank_pin_num), @@ -425,9 +428,12 @@ static void zynq_gpio_irq_mask(struct irq_data *irq_da= ta) static void zynq_gpio_irq_unmask(struct irq_data *irq_data) { unsigned int device_pin_num, bank_num, bank_pin_num; + const unsigned long offset =3D irqd_to_hwirq(irq_data); + struct gpio_chip *chip =3D irq_data_get_irq_chip_data(irq_data); struct zynq_gpio *gpio =3D gpiochip_get_data(irq_data_get_irq_chip_data(irq_data)); =20 + gpiochip_enable_irq(chip, offset); device_pin_num =3D irq_data->hwirq; zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); writel_relaxed(BIT(bank_pin_num), @@ -590,7 +596,7 @@ static void zynq_gpio_irq_relres(struct irq_data *d) } =20 /* irq chip descriptor */ -static struct irq_chip zynq_gpio_level_irqchip =3D { +static const struct irq_chip zynq_gpio_level_irqchip =3D { .name =3D DRIVER_NAME, .irq_enable =3D zynq_gpio_irq_enable, .irq_eoi =3D zynq_gpio_irq_ack, @@ -601,10 +607,11 @@ static struct irq_chip zynq_gpio_level_irqchip =3D { .irq_request_resources =3D zynq_gpio_irq_reqres, .irq_release_resources =3D zynq_gpio_irq_relres, .flags =3D IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED | - IRQCHIP_MASK_ON_SUSPEND, + IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, }; =20 -static struct irq_chip zynq_gpio_edge_irqchip =3D { +static const struct irq_chip zynq_gpio_edge_irqchip =3D { .name =3D DRIVER_NAME, .irq_enable =3D zynq_gpio_irq_enable, .irq_ack =3D zynq_gpio_irq_ack, @@ -614,7 +621,8 @@ static struct irq_chip zynq_gpio_edge_irqchip =3D { .irq_set_wake =3D zynq_gpio_set_wake, .irq_request_resources =3D zynq_gpio_irq_reqres, .irq_release_resources =3D zynq_gpio_irq_relres, - .flags =3D IRQCHIP_MASK_ON_SUSPEND, + .flags =3D IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, }; =20 static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio, @@ -962,7 +970,7 @@ static int zynq_gpio_probe(struct platform_device *pdev) =20 /* Set up the GPIO irqchip */ girq =3D &chip->irq; - girq->chip =3D &zynq_gpio_edge_irqchip; + gpio_irq_chip_set_chip(girq, &zynq_gpio_edge_irqchip); girq->parent_handler =3D zynq_gpio_irqhandler; girq->num_parents =3D 1; girq->parents =3D devm_kcalloc(&pdev->dev, 1, --=20 2.25.1