From nobody Sat Feb 7 09:46:32 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 817BCC77B73 for ; Tue, 6 Jun 2023 08:27:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237126AbjFFI1d (ORCPT ); Tue, 6 Jun 2023 04:27:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53690 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236717AbjFFI0g (ORCPT ); Tue, 6 Jun 2023 04:26:36 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 590D5E6A; Tue, 6 Jun 2023 01:26:27 -0700 (PDT) Date: Tue, 06 Jun 2023 08:26:22 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1686039983; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NoWRNjEC8b88vYCwf6jdo+1vsVv3EQG+11tseF6XQ8A=; b=2iC1u3USQKis14ujknjnJ3aJREaQ62iPvJBAvlben6nUpHSPnee8Tyc0yU3S6PjZkok9YW srRHYcxz3r4X7e39sB5h1sCIOU5mbugusKc5JVApAFm0sxJ++taVejQElJuqLPXer4kvM/ yl6n7f9J/M4UPA6cyAIyStqJbx1kOnE/mzj7SrVv1rTINrb9YdZcTUBBWPcSVrDqOSWwe3 LwJNdAGCtaCXuE3jjKa5skQc2U218aTVgDY0f5jE09P6f7xekVBrjUZ3da2F0o5g0gojkZ nBNeDRC23c5VYNy7InOg/3wqpQqQHjCAZ/RLHoEOawniDQ7vt9QVB+jeVUCjzQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1686039983; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NoWRNjEC8b88vYCwf6jdo+1vsVv3EQG+11tseF6XQ8A=; b=1agxxeaQdL7iw1+gI9nAJQH4LiMNUqkeGK+AXYSV720IaSdmZH0qoALUL+Lyi8bXv1fc8p iRenKF34nomAbPAQ== From: "tip-bot2 for Mark Rutland" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: locking/core] locking/atomic: sh: add preprocessor symbols Cc: Mark Rutland , "Peter Zijlstra (Intel)" , Kees Cook , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20230605070124.3741859-11-mark.rutland@arm.com> References: <20230605070124.3741859-11-mark.rutland@arm.com> MIME-Version: 1.0 Message-ID: <168603998249.404.992028948986196499.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the locking/core branch of tip: Commit-ID: 770345adc38485c688e5d832d82306a4c2da828c Gitweb: https://git.kernel.org/tip/770345adc38485c688e5d832d82306a4c= 2da828c Author: Mark Rutland AuthorDate: Mon, 05 Jun 2023 08:01:07 +01:00 Committer: Peter Zijlstra CommitterDate: Mon, 05 Jun 2023 09:57:16 +02:00 locking/atomic: sh: add preprocessor symbols Some atomics can be implemented in several different ways, e.g. FULL/ACQUIRE/RELEASE ordered atomics can be implemented in terms of RELAXED atomics, and ACQUIRE/RELEASE/RELAXED can be implemented in terms of FULL ordered atomics. Other atomics are optional, and don't exist in some configurations (e.g. not all architectures implement the 128-bit cmpxchg ops). Subsequent patches will require that architectures define a preprocessor symbol for any atomic (or ordering variant) which is optional. This will make the fallback ifdeffery more robust, and simplify future changes. Add the required definitions to arch/sh. Signed-off-by: Mark Rutland Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Kees Cook Link: https://lore.kernel.org/r/20230605070124.3741859-11-mark.rutland@arm.= com --- arch/sh/include/asm/atomic-grb.h | 9 +++++++++ arch/sh/include/asm/atomic-irq.h | 9 +++++++++ arch/sh/include/asm/atomic-llsc.h | 9 +++++++++ 3 files changed, 27 insertions(+) diff --git a/arch/sh/include/asm/atomic-grb.h b/arch/sh/include/asm/atomic-= grb.h index 059791f..cf1c10f 100644 --- a/arch/sh/include/asm/atomic-grb.h +++ b/arch/sh/include/asm/atomic-grb.h @@ -71,6 +71,11 @@ static inline int arch_atomic_fetch_##op(int i, atomic_t= *v) \ ATOMIC_OPS(add) ATOMIC_OPS(sub) =20 +#define arch_atomic_add_return arch_atomic_add_return +#define arch_atomic_sub_return arch_atomic_sub_return +#define arch_atomic_fetch_add arch_atomic_fetch_add +#define arch_atomic_fetch_sub arch_atomic_fetch_sub + #undef ATOMIC_OPS #define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_FETCH_OP(op) =20 @@ -78,6 +83,10 @@ ATOMIC_OPS(and) ATOMIC_OPS(or) ATOMIC_OPS(xor) =20 +#define arch_atomic_fetch_and arch_atomic_fetch_and +#define arch_atomic_fetch_or arch_atomic_fetch_or +#define arch_atomic_fetch_xor arch_atomic_fetch_xor + #undef ATOMIC_OPS #undef ATOMIC_FETCH_OP #undef ATOMIC_OP_RETURN diff --git a/arch/sh/include/asm/atomic-irq.h b/arch/sh/include/asm/atomic-= irq.h index 7665de9..b4090cc 100644 --- a/arch/sh/include/asm/atomic-irq.h +++ b/arch/sh/include/asm/atomic-irq.h @@ -55,6 +55,11 @@ static inline int arch_atomic_fetch_##op(int i, atomic_t= *v) \ ATOMIC_OPS(add, +=3D) ATOMIC_OPS(sub, -=3D) =20 +#define arch_atomic_add_return arch_atomic_add_return +#define arch_atomic_sub_return arch_atomic_sub_return +#define arch_atomic_fetch_add arch_atomic_fetch_add +#define arch_atomic_fetch_sub arch_atomic_fetch_sub + #undef ATOMIC_OPS #define ATOMIC_OPS(op, c_op) \ ATOMIC_OP(op, c_op) \ @@ -64,6 +69,10 @@ ATOMIC_OPS(and, &=3D) ATOMIC_OPS(or, |=3D) ATOMIC_OPS(xor, ^=3D) =20 +#define arch_atomic_fetch_and arch_atomic_fetch_and +#define arch_atomic_fetch_or arch_atomic_fetch_or +#define arch_atomic_fetch_xor arch_atomic_fetch_xor + #undef ATOMIC_OPS #undef ATOMIC_FETCH_OP #undef ATOMIC_OP_RETURN diff --git a/arch/sh/include/asm/atomic-llsc.h b/arch/sh/include/asm/atomic= -llsc.h index b63dcfb..9ef1fb1 100644 --- a/arch/sh/include/asm/atomic-llsc.h +++ b/arch/sh/include/asm/atomic-llsc.h @@ -73,6 +73,11 @@ static inline int arch_atomic_fetch_##op(int i, atomic_t= *v) \ ATOMIC_OPS(add) ATOMIC_OPS(sub) =20 +#define arch_atomic_add_return arch_atomic_add_return +#define arch_atomic_sub_return arch_atomic_sub_return +#define arch_atomic_fetch_add arch_atomic_fetch_add +#define arch_atomic_fetch_sub arch_atomic_fetch_sub + #undef ATOMIC_OPS #define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_FETCH_OP(op) =20 @@ -80,6 +85,10 @@ ATOMIC_OPS(and) ATOMIC_OPS(or) ATOMIC_OPS(xor) =20 +#define arch_atomic_fetch_and arch_atomic_fetch_and +#define arch_atomic_fetch_or arch_atomic_fetch_or +#define arch_atomic_fetch_xor arch_atomic_fetch_xor + #undef ATOMIC_OPS #undef ATOMIC_FETCH_OP #undef ATOMIC_OP_RETURN