From nobody Sun Feb 8 16:33:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B3A6C77B75 for ; Wed, 17 May 2023 21:56:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229604AbjEQV4l (ORCPT ); Wed, 17 May 2023 17:56:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50556 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229437AbjEQV4k (ORCPT ); Wed, 17 May 2023 17:56:40 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CE13126B7; Wed, 17 May 2023 14:56:38 -0700 (PDT) Date: Wed, 17 May 2023 21:56:35 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1684360596; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=ixxUzxjjfsnbP6oJRKzWVldOG+Bm+11hZ2PkJgmgdYo=; b=0jGoR85aFzxhzq0tU9nBOSeJlTjohhXR30cVa78jqmA8BFU/7o2Gm/LIOdIptebzyc0R9I ypFG9a3f+++CV8qN60FyKVZKFwT6hp2iChUCq9YteuKKNDxSuznV0TnNn8l6GHyBKh49gq O6SqsyfkGbK06J1HUSPTpM3WCh6ytpyKKgCDaSB1QyiER1+wMPtgSMMetFP7PhZvAIpxRI UQ2NVTSZsDRnkYAHEX0SrZBBzMmiCsYCeKIu8tgxhkzA0Tbmk0tNO+MHdCTSBh2+m1JO/D /2gG6cSD5CY/7o5sVTOAGvOoC9jdJboVEiLgAWwIqU4EuWCSyhg379y+n0D81A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1684360596; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=ixxUzxjjfsnbP6oJRKzWVldOG+Bm+11hZ2PkJgmgdYo=; b=8cRGbrwbfKERg06qduq1ebGfr6WDUrf2Ubjey4aY/K8AWm1XUEyXflK0pk5WYC1tUDiaYO hsqNpRLd5KkLApAw== From: "tip-bot2 for Dave Hansen" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/urgent] x86/mm: Avoid incomplete Global INVLPG flushes Cc: Dave Hansen , Thomas Gleixner , stable@vger.kernel.org, x86@kernel.org, linux-kernel@vger.kernel.org MIME-Version: 1.0 Message-ID: <168436059559.404.13934972543631851306.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the x86/urgent branch of tip: Commit-ID: ce0b15d11ad837fbacc5356941712218e38a0a83 Gitweb: https://git.kernel.org/tip/ce0b15d11ad837fbacc5356941712218e= 38a0a83 Author: Dave Hansen AuthorDate: Tue, 16 May 2023 12:24:25 -07:00 Committer: Dave Hansen CommitterDate: Wed, 17 May 2023 08:55:02 -07:00 x86/mm: Avoid incomplete Global INVLPG flushes The INVLPG instruction is used to invalidate TLB entries for a specified virtual address. When PCIDs are enabled, INVLPG is supposed to invalidate TLB entries for the specified address for both the current PCID *and* Global entries. (Note: Only kernel mappings set Global=3D1.) Unfortunately, some INVLPG implementations can leave Global translations unflushed when PCIDs are enabled. As a workaround, never enable PCIDs on affected processors. I expect there to eventually be microcode mitigations to replace this software workaround. However, the exact version numbers where that will happen are not known today. Once the version numbers are set in stone, the processor list can be tweaked to only disable PCIDs on affected processors with affected microcode. Note: if anyone wants a quick fix that doesn't require patching, just stick 'nopcid' on your kernel command-line. Signed-off-by: Dave Hansen Reviewed-by: Thomas Gleixner Cc: stable@vger.kernel.org --- arch/x86/mm/init.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index 3cdac0f..8192452 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -9,6 +9,7 @@ #include =20 #include +#include #include #include #include @@ -261,6 +262,24 @@ static void __init probe_page_size_mask(void) } } =20 +#define INTEL_MATCH(_model) { .vendor =3D X86_VENDOR_INTEL, \ + .family =3D 6, \ + .model =3D _model, \ + } +/* + * INVLPG may not properly flush Global entries + * on these CPUs when PCIDs are enabled. + */ +static const struct x86_cpu_id invlpg_miss_ids[] =3D { + INTEL_MATCH(INTEL_FAM6_ALDERLAKE ), + INTEL_MATCH(INTEL_FAM6_ALDERLAKE_L ), + INTEL_MATCH(INTEL_FAM6_ALDERLAKE_N ), + INTEL_MATCH(INTEL_FAM6_RAPTORLAKE ), + INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_P), + INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_S), + {} +}; + static void setup_pcid(void) { if (!IS_ENABLED(CONFIG_X86_64)) @@ -269,6 +288,12 @@ static void setup_pcid(void) if (!boot_cpu_has(X86_FEATURE_PCID)) return; =20 + if (x86_match_cpu(invlpg_miss_ids)) { + pr_info("Incomplete global flushes, disabling PCID"); + setup_clear_cpu_cap(X86_FEATURE_PCID); + return; + } + if (boot_cpu_has(X86_FEATURE_PGE)) { /* * This can't be cr4_set_bits_and_update_boot() -- the