From nobody Sun Feb 8 11:21:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72999C77B75 for ; Tue, 16 May 2023 09:11:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231923AbjEPJLt (ORCPT ); Tue, 16 May 2023 05:11:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46162 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231825AbjEPJKH (ORCPT ); Tue, 16 May 2023 05:10:07 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E6CAC46B3; Tue, 16 May 2023 02:10:04 -0700 (PDT) Date: Tue, 16 May 2023 09:10:00 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1684228201; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7OQzWFkolSQOsYYqsopCAhFmKyFXUNICSAqEkkq6TPM=; b=CAGLXJfz/VTiIvUNFib/jcfAdQHMkWT4UzffgdXqUOakBbMp3nUjAa9TiXPDvXSCe0pSwn GMnWq/AOzFb2Zi3exTyHcXRIVtPfzIqVHnRxks5ik8+1N2K1R3k8/54oCEIsQGLWiPcKNM ZvlKmYXxXht5NzYDYghE9BbcjXmyWGZZYMlwLBPPQ7ZZ154SV740vkWSkXy1W/39eNRhMn 3wdVBOAumpeSOG6Boso7imJFhGLxQnXSU+9sZn0hZMUesSleHZCT+zbb201RH4eFz4xh2t m4i+HX315mwqGTS+aGjSuKRTqYdKl5sNOmrugOEIwK3HN4dUlYHbCZii7oM59A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1684228201; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7OQzWFkolSQOsYYqsopCAhFmKyFXUNICSAqEkkq6TPM=; b=u3rck7Jq3dXi9fDsHqNFllI13hwWSNrq8c3H/sN07OnzZReOd/XsZnXCjvQTkYsbqwo4a4 45RslNeuW/hdzDAg== From: "tip-bot2 for Thomas Gleixner" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: smp/core] x86/cpu/cacheinfo: Remove cpu_callout_mask dependency Cc: Thomas Gleixner , "Peter Zijlstra (Intel)" , Michael Kelley , Oleksandr Natalenko , Helge Deller , "Guilherme G. Piccoli" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20230512205256.035041005@linutronix.de> References: <20230512205256.035041005@linutronix.de> MIME-Version: 1.0 Message-ID: <168422820087.404.16340728818249846173.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the smp/core branch of tip: Commit-ID: a32226fa3b7d33d380494cf94cf1d4f8ebb70004 Gitweb: https://git.kernel.org/tip/a32226fa3b7d33d380494cf94cf1d4f8e= bb70004 Author: Thomas Gleixner AuthorDate: Fri, 12 May 2023 23:07:14 +02:00 Committer: Peter Zijlstra CommitterDate: Mon, 15 May 2023 13:44:52 +02:00 x86/cpu/cacheinfo: Remove cpu_callout_mask dependency cpu_callout_mask is used for the stop machine based MTRR/PAT init. In preparation of moving the BP/AP synchronization to the core hotplug code, use a private CPU mask for cacheinfo and manage it in the starting/dying hotplug state. Signed-off-by: Thomas Gleixner Signed-off-by: Peter Zijlstra (Intel) Tested-by: Michael Kelley Tested-by: Oleksandr Natalenko Tested-by: Helge Deller # parisc Tested-by: Guilherme G. Piccoli # Steam Deck Link: https://lore.kernel.org/r/20230512205256.035041005@linutronix.de --- arch/x86/kernel/cpu/cacheinfo.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 4063e89..8f86eac 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -39,6 +39,8 @@ DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_= map); /* Shared L2 cache maps */ DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_l2c_shared_map); =20 +static cpumask_var_t cpu_cacheinfo_mask; + /* Kernel controls MTRR and/or PAT MSRs. */ unsigned int memory_caching_control __ro_after_init; =20 @@ -1172,8 +1174,10 @@ void cache_bp_restore(void) cache_cpu_init(); } =20 -static int cache_ap_init(unsigned int cpu) +static int cache_ap_online(unsigned int cpu) { + cpumask_set_cpu(cpu, cpu_cacheinfo_mask); + if (!memory_caching_control || get_cache_aps_delayed_init()) return 0; =20 @@ -1191,11 +1195,17 @@ static int cache_ap_init(unsigned int cpu) * lock to prevent MTRR entry changes */ stop_machine_from_inactive_cpu(cache_rendezvous_handler, NULL, - cpu_callout_mask); + cpu_cacheinfo_mask); =20 return 0; } =20 +static int cache_ap_offline(unsigned int cpu) +{ + cpumask_clear_cpu(cpu, cpu_cacheinfo_mask); + return 0; +} + /* * Delayed cache initialization for all AP's */ @@ -1210,9 +1220,12 @@ void cache_aps_init(void) =20 static int __init cache_ap_register(void) { + zalloc_cpumask_var(&cpu_cacheinfo_mask, GFP_KERNEL); + cpumask_set_cpu(smp_processor_id(), cpu_cacheinfo_mask); + cpuhp_setup_state_nocalls(CPUHP_AP_CACHECTRL_STARTING, "x86/cachectrl:starting", - cache_ap_init, NULL); + cache_ap_online, cache_ap_offline); return 0; } -core_initcall(cache_ap_register); +early_initcall(cache_ap_register);