From nobody Wed Feb 11 09:20:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5F08C7EE22 for ; Wed, 10 May 2023 13:26:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237066AbjEJN0G (ORCPT ); Wed, 10 May 2023 09:26:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60582 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236738AbjEJNZ6 (ORCPT ); Wed, 10 May 2023 09:25:58 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 767345B96; Wed, 10 May 2023 06:25:55 -0700 (PDT) Date: Wed, 10 May 2023 13:25:52 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1683725153; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2wCDCMVLVHkAwMTT4agPvZQd6bXtY1uPlo5JBSddpyI=; b=4qNVnhTCFEUDKGHJXbKI5a0lwGqp+R7m8fkL5mrAr2GhI7eeOextrxCcnbK3WQM1+XbYiX LzpUX4JSul74/EPXsTMZ69JLUW1nRj5RYoeYxTUwRXj0LJv0kTHF4R8FhgbsZn7/rRSZ+p mJhyGLnYdfUWJyvROfzSCvgU8CCPzxzrEy2DHTUYsC2fsT2BzcQCztmw0hWo+Ndd/e53Gm wjnCw62L2eiWOA+FPGmz0gH72D7sLhrI9iEgByKeMb02tpH22dDf5Jhsasek2YrgbMZucc Sj0W5SOscUOD8OlrkBRsQSfeaa4fqq9JUqBryA+eWaiP5Jl4KDcQDtp+kpVvbA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1683725153; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2wCDCMVLVHkAwMTT4agPvZQd6bXtY1uPlo5JBSddpyI=; b=4SU/X6289E2I+zi/BXaDKmo66YETFiIl/mrkdl/m66YRuh9clYQMySPy0rdf9rflyP7LnU ItVgm5ua0xVgUSCQ== From: "tip-bot2 for Kan Liang" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/urgent] perf/x86/intel/ds: Flush PEBS DS when changing PEBS_DATA_CFG Cc: Stephane Eranian , "Peter Zijlstra (Intel)" , Kan Liang , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20230421184529.3320912-1-kan.liang@linux.intel.com> References: <20230421184529.3320912-1-kan.liang@linux.intel.com> MIME-Version: 1.0 Message-ID: <168372515266.404.11587715767446878831.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the perf/urgent branch of tip: Commit-ID: b752ea0c28e3f7f0aaaad6abf84f735eebc37a60 Gitweb: https://git.kernel.org/tip/b752ea0c28e3f7f0aaaad6abf84f735ee= bc37a60 Author: Kan Liang AuthorDate: Fri, 21 Apr 2023 11:45:28 -07:00 Committer: Peter Zijlstra CommitterDate: Mon, 08 May 2023 10:58:27 +02:00 perf/x86/intel/ds: Flush PEBS DS when changing PEBS_DATA_CFG Several similar kernel warnings can be triggered, [56605.607840] CPU0 PEBS record size 0, expected 32, config 0 cpuc->recor= d_size=3D208 when the below commands are running in parallel for a while on SPR. while true; do perf record --no-buildid -a --intr-regs=3DAX \ -e cpu/event=3D0xd0,umask=3D0x81/pp \ -c 10003 -o /dev/null ./triad; done & while true; do perf record -o /tmp/out -W -d \ -e '{ld_blocks.store_forward:period=3D1000000, \ MEM_TRANS_RETIRED.LOAD_LATENCY:u:precise=3D2:ldlat= =3D4}' \ -c 1037 ./triad; done The triad program is just the generation of loads/stores. The warnings are triggered when an unexpected PEBS record (with a different config and size) is found. A system-wide PEBS event with the large PEBS config may be enabled during a context switch. Some PEBS records for the system-wide PEBS may be generated while the old task is sched out but the new one hasn't been sched in yet. When the new task is sched in, the cpuc->pebs_record_size may be updated for the per-task PEBS events. So the existing system-wide PEBS records have a different size from the later PEBS records. The PEBS buffer should be flushed right before the hardware is reprogrammed. The new size and threshold should be updated after the old buffer has been flushed. Reported-by: Stephane Eranian Suggested-by: Peter Zijlstra (Intel) Signed-off-by: Kan Liang Signed-off-by: Peter Zijlstra (Intel) Link: https://lkml.kernel.org/r/20230421184529.3320912-1-kan.liang@linux.in= tel.com --- arch/x86/events/intel/ds.c | 56 +++++++++++++++++------------- arch/x86/include/asm/perf_event.h | 3 ++- 2 files changed, 35 insertions(+), 24 deletions(-) diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index a2e566e..df88576 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -1229,12 +1229,14 @@ pebs_update_state(bool needed_cb, struct cpu_hw_eve= nts *cpuc, struct perf_event *event, bool add) { struct pmu *pmu =3D event->pmu; + /* * Make sure we get updated with the first PEBS * event. It will trigger also during removal, but * that does not hurt: */ - bool update =3D cpuc->n_pebs =3D=3D 1; + if (cpuc->n_pebs =3D=3D 1) + cpuc->pebs_data_cfg =3D PEBS_UPDATE_DS_SW; =20 if (needed_cb !=3D pebs_needs_sched_cb(cpuc)) { if (!needed_cb) @@ -1242,7 +1244,7 @@ pebs_update_state(bool needed_cb, struct cpu_hw_event= s *cpuc, else perf_sched_cb_dec(pmu); =20 - update =3D true; + cpuc->pebs_data_cfg |=3D PEBS_UPDATE_DS_SW; } =20 /* @@ -1252,24 +1254,13 @@ pebs_update_state(bool needed_cb, struct cpu_hw_eve= nts *cpuc, if (x86_pmu.intel_cap.pebs_baseline && add) { u64 pebs_data_cfg; =20 - /* Clear pebs_data_cfg and pebs_record_size for first PEBS. */ - if (cpuc->n_pebs =3D=3D 1) { - cpuc->pebs_data_cfg =3D 0; - cpuc->pebs_record_size =3D sizeof(struct pebs_basic); - } - pebs_data_cfg =3D pebs_update_adaptive_cfg(event); - - /* Update pebs_record_size if new event requires more data. */ - if (pebs_data_cfg & ~cpuc->pebs_data_cfg) { - cpuc->pebs_data_cfg |=3D pebs_data_cfg; - adaptive_pebs_record_size_update(); - update =3D true; - } + /* + * Be sure to update the thresholds when we change the record. + */ + if (pebs_data_cfg & ~cpuc->pebs_data_cfg) + cpuc->pebs_data_cfg |=3D pebs_data_cfg | PEBS_UPDATE_DS_SW; } - - if (update) - pebs_update_threshold(cpuc); } =20 void intel_pmu_pebs_add(struct perf_event *event) @@ -1326,9 +1317,17 @@ static void intel_pmu_pebs_via_pt_enable(struct perf= _event *event) wrmsrl(base + idx, value); } =20 +static inline void intel_pmu_drain_large_pebs(struct cpu_hw_events *cpuc) +{ + if (cpuc->n_pebs =3D=3D cpuc->n_large_pebs && + cpuc->n_pebs !=3D cpuc->n_pebs_via_pt) + intel_pmu_drain_pebs_buffer(); +} + void intel_pmu_pebs_enable(struct perf_event *event) { struct cpu_hw_events *cpuc =3D this_cpu_ptr(&cpu_hw_events); + u64 pebs_data_cfg =3D cpuc->pebs_data_cfg & ~PEBS_UPDATE_DS_SW; struct hw_perf_event *hwc =3D &event->hw; struct debug_store *ds =3D cpuc->ds; unsigned int idx =3D hwc->idx; @@ -1344,11 +1343,22 @@ void intel_pmu_pebs_enable(struct perf_event *event) =20 if (x86_pmu.intel_cap.pebs_baseline) { hwc->config |=3D ICL_EVENTSEL_ADAPTIVE; - if (cpuc->pebs_data_cfg !=3D cpuc->active_pebs_data_cfg) { - wrmsrl(MSR_PEBS_DATA_CFG, cpuc->pebs_data_cfg); - cpuc->active_pebs_data_cfg =3D cpuc->pebs_data_cfg; + if (pebs_data_cfg !=3D cpuc->active_pebs_data_cfg) { + /* + * drain_pebs() assumes uniform record size; + * hence we need to drain when changing said + * size. + */ + intel_pmu_drain_large_pebs(cpuc); + adaptive_pebs_record_size_update(); + wrmsrl(MSR_PEBS_DATA_CFG, pebs_data_cfg); + cpuc->active_pebs_data_cfg =3D pebs_data_cfg; } } + if (cpuc->pebs_data_cfg & PEBS_UPDATE_DS_SW) { + cpuc->pebs_data_cfg =3D pebs_data_cfg; + pebs_update_threshold(cpuc); + } =20 if (idx >=3D INTEL_PMC_IDX_FIXED) { if (x86_pmu.intel_cap.pebs_format < 5) @@ -1391,9 +1401,7 @@ void intel_pmu_pebs_disable(struct perf_event *event) struct cpu_hw_events *cpuc =3D this_cpu_ptr(&cpu_hw_events); struct hw_perf_event *hwc =3D &event->hw; =20 - if (cpuc->n_pebs =3D=3D cpuc->n_large_pebs && - cpuc->n_pebs !=3D cpuc->n_pebs_via_pt) - intel_pmu_drain_pebs_buffer(); + intel_pmu_drain_large_pebs(cpuc); =20 cpuc->pebs_enabled &=3D ~(1ULL << hwc->idx); =20 diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_= event.h index 8fc15ed..abf0988 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -121,6 +121,9 @@ #define PEBS_DATACFG_LBRS BIT_ULL(3) #define PEBS_DATACFG_LBR_SHIFT 24 =20 +/* Steal the highest bit of pebs_data_cfg for SW usage */ +#define PEBS_UPDATE_DS_SW BIT_ULL(63) + /* * Intel "Architectural Performance Monitoring" CPUID * detection/enumeration details: