From nobody Wed Feb 11 13:54:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2F8DC76196 for ; Fri, 7 Apr 2023 02:15:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240323AbjDGCPO (ORCPT ); Thu, 6 Apr 2023 22:15:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50982 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239932AbjDGCPG (ORCPT ); Thu, 6 Apr 2023 22:15:06 -0400 Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 580B610C1 for ; Thu, 6 Apr 2023 19:15:05 -0700 (PDT) Received: from loongson.cn (unknown [113.200.148.30]) by gateway (Coremail) with SMTP id _____8Axz_+ofC9kmakXAA--.36751S3; Fri, 07 Apr 2023 10:15:04 +0800 (CST) Received: from linux.localdomain (unknown [113.200.148.30]) by localhost.localdomain (Coremail) with SMTP id AQAAf8DxSL2lfC9k2cEXAA--.21395S4; Fri, 07 Apr 2023 10:15:04 +0800 (CST) From: Tiezhu Yang To: Huacai Chen , WANG Xuerui Cc: loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, loongson-kernel@lists.loongnix.cn Subject: [RFC PATCH 2/3] LoongArch: Add larch_insn_gen_break() to generate break insn Date: Fri, 7 Apr 2023 10:15:00 +0800 Message-Id: <1680833701-1727-3-git-send-email-yangtiezhu@loongson.cn> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1680833701-1727-1-git-send-email-yangtiezhu@loongson.cn> References: <1680833701-1727-1-git-send-email-yangtiezhu@loongson.cn> X-CM-TRANSID: AQAAf8DxSL2lfC9k2cEXAA--.21395S4 X-CM-SenderInfo: p1dqw3xlh2x3gn0dqz5rrqw2lrqou0/ X-Coremail-Antispam: 1Uk129KBjvJXoWxKryDtr4ruF4xKry7Jw4DCFg_yoW7WF4UpF srAwn5Jr48Wr93Gr9rJws8Zr15trs3WwsFqFsIk3yfCFW7Xwn8tF18KryqvF90k3ykGFWI q3Waqw1UZ3W5A3DanT9S1TB71UUUUUJqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj qI5I8CrVACY4xI64kE6c02F40Ex7xfYxn0WfASr-VFAUDa7-sFnT9fnUUIcSsGvfJTRUUU b3kYFVCjjxCrM7AC8VAFwI0_Jr0_Gr1l1xkIjI8I6I8E6xAIw20EY4v20xvaj40_Wr0E3s 1l1IIY67AEw4v_Jrv_JF1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2x7M28EF7xv wVC0I7IYx2IY67AKxVW5JVW7JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwA2z4 x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv6xkF7I0E14v26F4UJVW0owAa w2AFwI0_Jrv_JF1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44 I27wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jw0_WrylYx0Ex4A2 jsIE14v26r4j6F4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCF04k20x vY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwCFI7km07C267AKxVWUXVWUAwC20s02 6c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF 0_Jw1lIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVW8JVW5JwCI42IY6xIIjxv20xvE c7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14 v26r4j6F4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x 07jz2NtUUUUU= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There exist various break insns such as BRK_KPROBE_BP, BRK_KPROBE_SSTEPBP, BRK_UPROBE_BP and BRK_UPROBE_XOLBP, add larch_insn_gen_break() to generate break insns simpler and easier. This is preparation for later patch, no functionality change. Signed-off-by: Tiezhu Yang --- arch/loongarch/include/asm/inst.h | 30 +++++++++++++++++++++++++++--- arch/loongarch/include/asm/kprobes.h | 2 +- arch/loongarch/kernel/inst.c | 9 +++++++++ arch/loongarch/kernel/kprobes.c | 17 +++-------------- 4 files changed, 40 insertions(+), 18 deletions(-) diff --git a/arch/loongarch/include/asm/inst.h b/arch/loongarch/include/asm= /inst.h index af494b5..a0fce06 100644 --- a/arch/loongarch/include/asm/inst.h +++ b/arch/loongarch/include/asm/inst.h @@ -409,8 +409,12 @@ static inline bool is_self_loop_ins(union loongarch_in= struction *ip, struct pt_r void simu_pc(struct pt_regs *regs, union loongarch_instruction insn); void simu_branch(struct pt_regs *regs, union loongarch_instruction insn); =20 -static inline bool insns_not_supported(union loongarch_instruction insn) +static inline bool insns_not_supported(u32 code) { + union loongarch_instruction insn; + + insn.word =3D code; + switch (insn.reg2i14_format.opcode) { case llw_op: case lld_op: @@ -429,8 +433,12 @@ static inline bool insns_not_supported(union loongarch= _instruction insn) return false; } =20 -static inline bool insns_need_simulation(union loongarch_instruction insn) +static inline bool insns_need_simulation(u32 code) { + union loongarch_instruction insn; + + insn.word =3D code; + if (is_pc_ins(&insn)) return true; =20 @@ -440,8 +448,12 @@ static inline bool insns_need_simulation(union loongar= ch_instruction insn) return false; } =20 -static inline void arch_simulate_insn(union loongarch_instruction insn, st= ruct pt_regs *regs) +static inline void arch_simulate_insn(u32 code, struct pt_regs *regs) { + union loongarch_instruction insn; + + insn.word =3D code; + if (is_pc_ins(&insn)) simu_pc(regs, insn); else if (is_branch_ins(&insn)) @@ -456,6 +468,8 @@ u32 larch_insn_gen_nop(void); u32 larch_insn_gen_b(unsigned long pc, unsigned long dest); u32 larch_insn_gen_bl(unsigned long pc, unsigned long dest); =20 +u32 larch_insn_gen_break(int imm); + u32 larch_insn_gen_or(enum loongarch_gpr rd, enum loongarch_gpr rj, enum l= oongarch_gpr rk); u32 larch_insn_gen_move(enum loongarch_gpr rd, enum loongarch_gpr rj); =20 @@ -474,6 +488,16 @@ static inline bool unsigned_imm_check(unsigned long va= l, unsigned int bit) return val < (1UL << bit); } =20 +#define DEF_EMIT_REG0I15_FORMAT(NAME, OP) \ +static inline void emit_##NAME(union loongarch_instruction *insn, \ + int imm) \ +{ \ + insn->reg0i15_format.opcode =3D OP; \ + insn->reg0i15_format.immediate =3D imm; \ +} + +DEF_EMIT_REG0I15_FORMAT(break, break_op) + #define DEF_EMIT_REG0I26_FORMAT(NAME, OP) \ static inline void emit_##NAME(union loongarch_instruction *insn, \ int offset) \ diff --git a/arch/loongarch/include/asm/kprobes.h b/arch/loongarch/include/= asm/kprobes.h index 798020a..7ef7a0f 100644 --- a/arch/loongarch/include/asm/kprobes.h +++ b/arch/loongarch/include/asm/kprobes.h @@ -22,7 +22,7 @@ do { \ =20 #define kretprobe_blacklist_size 0 =20 -typedef union loongarch_instruction kprobe_opcode_t; +typedef u32 kprobe_opcode_t; =20 /* Architecture specific copy of original instruction */ struct arch_specific_insn { diff --git a/arch/loongarch/kernel/inst.c b/arch/loongarch/kernel/inst.c index 258ef26..31b8efe 100644 --- a/arch/loongarch/kernel/inst.c +++ b/arch/loongarch/kernel/inst.c @@ -208,6 +208,15 @@ u32 larch_insn_gen_bl(unsigned long pc, unsigned long = dest) return insn.word; } =20 +u32 larch_insn_gen_break(int imm) +{ + union loongarch_instruction insn; + + emit_break(&insn, imm); + + return insn.word; +} + u32 larch_insn_gen_or(enum loongarch_gpr rd, enum loongarch_gpr rj, enum l= oongarch_gpr rk) { union loongarch_instruction insn; diff --git a/arch/loongarch/kernel/kprobes.c b/arch/loongarch/kernel/kprobe= s.c index 08c78d2..a5c3712 100644 --- a/arch/loongarch/kernel/kprobes.c +++ b/arch/loongarch/kernel/kprobes.c @@ -4,19 +4,8 @@ #include #include =20 -static const union loongarch_instruction breakpoint_insn =3D { - .reg0i15_format =3D { - .opcode =3D break_op, - .immediate =3D BRK_KPROBE_BP, - } -}; - -static const union loongarch_instruction singlestep_insn =3D { - .reg0i15_format =3D { - .opcode =3D break_op, - .immediate =3D BRK_KPROBE_SSTEPBP, - } -}; +#define breakpoint_insn larch_insn_gen_break(BRK_KPROBE_BP) +#define singlestep_insn larch_insn_gen_break(BRK_KPROBE_SSTEPBP) =20 DEFINE_PER_CPU(struct kprobe *, current_kprobe); DEFINE_PER_CPU(struct kprobe_ctlblk, kprobe_ctlblk); @@ -253,7 +242,7 @@ bool kprobe_breakpoint_handler(struct pt_regs *regs) } } =20 - if (addr->word !=3D breakpoint_insn.word) { + if (*addr !=3D breakpoint_insn) { /* * The breakpoint instruction was removed right * after we hit it. Another cpu has removed --=20 2.1.0