From nobody Sun Feb 8 15:46:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D532C6FD1D for ; Mon, 20 Mar 2023 16:50:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232532AbjCTQu2 (ORCPT ); Mon, 20 Mar 2023 12:50:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41822 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232474AbjCTQtc (ORCPT ); Mon, 20 Mar 2023 12:49:32 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 659B1618D; Mon, 20 Mar 2023 09:42:06 -0700 (PDT) Date: Mon, 20 Mar 2023 16:39:29 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1679330369; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=IyWmU3LDAqcjF6F6Xb+HcI6kQKClv30nzS+jjqZZwXU=; b=vs4o1swuV7Qs9VTfP134h6nDbBrAnM8a+dORwAUJaGA+9wiIqtAz+XyUzfwuqUEUNpRiTH fgJf5gttUbo4bEBTNCN41dJkq+UdC3ouuRW+O2hKgY4T2X67i9Rak7J8yW+ulj3CYu49CO 103SsXpP3R43yyrfutmKj14AgD201xa1+IC/B7UBtQT6KEiWWRLpBwqTettWE/lZH9G/Da Hb/SE88AhPGP53SoN21z7gHE++ZR+bcd42YqO2ScDt7j1nb76r3IK86Yk0Vjmw32LaO6QQ 0lXAKuGvhPHzyo8ahToPuMbKqlSMZC0GqQ1URXmEAgOE+Yh+yBOWFVpj3RAv4A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1679330369; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=IyWmU3LDAqcjF6F6Xb+HcI6kQKClv30nzS+jjqZZwXU=; b=VdYQxu1GjN9Pmnl1ktkGHvh4n8h9RsI9b42y5Bxvs/4NuQFHyySWVV8pDLo3T+4/t3f+Qv y0Ww6iwfshs9SaDQ== From: "tip-bot2 for Rick Edgecombe" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/shstk] x86/mm: Remove _PAGE_DIRTY from kernel RO pages Cc: "Yu-cheng Yu" , Rick Edgecombe , Dave Hansen , "Borislav Petkov (AMD)" , Kees Cook , "Mike Rapoport (IBM)" , Pengfei Xu , John Allen , x86@kernel.org, linux-kernel@vger.kernel.org MIME-Version: 1.0 Message-ID: <167933036914.5837.4622429665589179520.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the x86/shstk branch of tip: Commit-ID: 4cecb5493945804d039ac918006465400f6418ee Gitweb: https://git.kernel.org/tip/4cecb5493945804d039ac918006465400= f6418ee Author: Rick Edgecombe AuthorDate: Sat, 18 Mar 2023 17:15:04 -07:00 Committer: Dave Hansen CommitterDate: Mon, 20 Mar 2023 09:01:08 -07:00 x86/mm: Remove _PAGE_DIRTY from kernel RO pages New processors that support Shadow Stack regard Write=3D0,Dirty=3D1 PTEs as shadow stack pages. In normal cases, it can be helpful to create Write=3D1 PTEs as also Dirty= =3D1 if HW dirty tracking is not needed, because if the Dirty bit is not already set the CPU has to set Dirty=3D1 when the memory gets written to. This creates additional work for the CPU. So traditional wisdom was to simply set the Dirty bit whenever you didn't care about it. However, it was never really very helpful for read-only kernel memory. When CR4.CET=3D1 and IA32_S_CET.SH_STK_EN=3D1, some instructions can write = to such supervisor memory. The kernel does not set IA32_S_CET.SH_STK_EN, so avoiding kernel Write=3D0,Dirty=3D1 memory is not strictly needed for any functional reason. But having Write=3D0,Dirty=3D1 kernel memory doesn't have any functional benefit either, so to reduce ambiguity between shadow stack and regular Write=3D0 pages, remove Dirty=3D1 from any kernel Write=3D0 PTE= s. Co-developed-by: Yu-cheng Yu Signed-off-by: Yu-cheng Yu Signed-off-by: Rick Edgecombe Signed-off-by: Dave Hansen Reviewed-by: Borislav Petkov (AMD) Reviewed-by: Kees Cook Acked-by: Mike Rapoport (IBM) Tested-by: Pengfei Xu Tested-by: John Allen Tested-by: Kees Cook Link: https://lore.kernel.org/all/20230319001535.23210-10-rick.p.edgecombe%= 40intel.com --- arch/x86/include/asm/pgtable_types.h | 6 +++--- arch/x86/mm/pat/set_memory.c | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pg= table_types.h index 447d4be..0646ad0 100644 --- a/arch/x86/include/asm/pgtable_types.h +++ b/arch/x86/include/asm/pgtable_types.h @@ -192,10 +192,10 @@ enum page_cache_mode { #define _KERNPG_TABLE (__PP|__RW| 0|___A| 0|___D| 0| 0| _ENC) #define _PAGE_TABLE_NOENC (__PP|__RW|_USR|___A| 0|___D| 0| 0) #define _PAGE_TABLE (__PP|__RW|_USR|___A| 0|___D| 0| 0| _ENC) -#define __PAGE_KERNEL_RO (__PP| 0| 0|___A|__NX|___D| 0|___G) -#define __PAGE_KERNEL_ROX (__PP| 0| 0|___A| 0|___D| 0|___G) +#define __PAGE_KERNEL_RO (__PP| 0| 0|___A|__NX| 0| 0|___G) +#define __PAGE_KERNEL_ROX (__PP| 0| 0|___A| 0| 0| 0|___G) #define __PAGE_KERNEL_NOCACHE (__PP|__RW| 0|___A|__NX|___D| 0|___G| _= _NC) -#define __PAGE_KERNEL_VVAR (__PP| 0|_USR|___A|__NX|___D| 0|___G) +#define __PAGE_KERNEL_VVAR (__PP| 0|_USR|___A|__NX| 0| 0|___G) #define __PAGE_KERNEL_LARGE (__PP|__RW| 0|___A|__NX|___D|_PSE|___G) #define __PAGE_KERNEL_LARGE_EXEC (__PP|__RW| 0|___A| 0|___D|_PSE|___G) #define __PAGE_KERNEL_WP (__PP|__RW| 0|___A|__NX|___D| 0|___G| __WP) diff --git a/arch/x86/mm/pat/set_memory.c b/arch/x86/mm/pat/set_memory.c index 356758b..1b5c0dc 100644 --- a/arch/x86/mm/pat/set_memory.c +++ b/arch/x86/mm/pat/set_memory.c @@ -2073,12 +2073,12 @@ int set_memory_nx(unsigned long addr, int numpages) =20 int set_memory_ro(unsigned long addr, int numpages) { - return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0); + return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW | _PAGE_= DIRTY), 0); } =20 int set_memory_rox(unsigned long addr, int numpages) { - pgprot_t clr =3D __pgprot(_PAGE_RW); + pgprot_t clr =3D __pgprot(_PAGE_RW | _PAGE_DIRTY); =20 if (__supported_pte_mask & _PAGE_NX) clr.pgprot |=3D _PAGE_NX;