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[46.138.144.249]) by smtp.gmail.com with ESMTPSA id f6-20020ac25326000000b004d85f2acd8esm710065lfh.295.2023.03.12.11.11.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Mar 2023 11:11:17 -0700 (PDT) Message-Id: <1678644516.665314-2-sleirsgoevy@gmail.com> In-Reply-To: <1678644516.665314-0-sleirsgoevy@gmail.com> From: Sergey Lisov Date: Sun, 12 Mar 2023 20:58:50 +0300 Subject: [PATCH v5 2/3] mmc: dw_mmc: add an option to force 32-bit access to 64-bit FIFO To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Alim Akhtar , Jaehoon Chung Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Some Samsung Exynos boards using the arm64 architecture have DW MMC controllers configured for a 32-bit data bus but a 64-bit FIFO. On these systems the 64-bit FIFO registers must be accessed in two 32-bit halves. --- drivers/mmc/host/dw_mmc-exynos.c | 43 ++++++++++- drivers/mmc/host/dw_mmc.c | 122 ++++++++++++++++++++++++++++++- drivers/mmc/host/dw_mmc.h | 2 + 3 files changed, 164 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exy= nos.c index 9f20ac524..b4c0ba2eb 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c @@ -28,6 +28,8 @@ enum dw_mci_exynos_type { DW_MCI_TYPE_EXYNOS5420_SMU, DW_MCI_TYPE_EXYNOS7, DW_MCI_TYPE_EXYNOS7_SMU, + DW_MCI_TYPE_EXYNOS78XX, + DW_MCI_TYPE_EXYNOS78XX_SMU, DW_MCI_TYPE_ARTPEC8, }; =20 @@ -70,6 +72,12 @@ static struct dw_mci_exynos_compatible { }, { .compatible =3D "samsung,exynos7-dw-mshc-smu", .ctrl_type =3D DW_MCI_TYPE_EXYNOS7_SMU, + }, { + .compatible =3D "samsung,exynos7885-dw-mshc", + .ctrl_type =3D DW_MCI_TYPE_EXYNOS78XX, + }, { + .compatible =3D "samsung,exynos7885-dw-mshc-smu", + .ctrl_type =3D DW_MCI_TYPE_EXYNOS78XX_SMU, }, { .compatible =3D "axis,artpec8-dw-mshc", .ctrl_type =3D DW_MCI_TYPE_ARTPEC8, @@ -86,6 +94,8 @@ static inline u8 dw_mci_exynos_get_ciu_div(struct dw_mci = *host) return EXYNOS4210_FIXED_CIU_CLK_DIV; else if (priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type =3D=3D DW_MCI_TYPE_ARTPEC8) return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL64)) + 1; else @@ -101,7 +111,8 @@ static void dw_mci_exynos_config_smu(struct dw_mci *hos= t) * set for non-ecryption mode at this time. */ if (priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS5420_SMU || - priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7_SMU) { + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX_SMU) { mci_writel(host, MPSBEGIN0, 0); mci_writel(host, MPSEND0, SDMMC_ENDING_SEC_NR_MAX); mci_writel(host, MPSCTRL0, SDMMC_MPSCTRL_SECURE_WRITE_BIT | @@ -127,6 +138,12 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host) DQS_CTRL_GET_RD_DELAY(priv->saved_strobe_ctrl); } =20 + if (priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX_SMU) { + /* Quirk needed for certain Exynos SoCs */ + host->quirks |=3D DW_MMC_QUIRK_FIFO64_32; + } + if (priv->ctrl_type =3D=3D DW_MCI_TYPE_ARTPEC8) { /* Quirk needed for the ARTPEC-8 SoC */ host->quirks |=3D DW_MMC_QUIRK_EXTENDED_TMOUT; @@ -144,6 +161,8 @@ static void dw_mci_exynos_set_clksel_timing(struct dw_m= ci *host, u32 timing) =20 if (priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type =3D=3D DW_MCI_TYPE_ARTPEC8) clksel =3D mci_readl(host, CLKSEL64); else @@ -153,6 +172,8 @@ static void dw_mci_exynos_set_clksel_timing(struct dw_m= ci *host, u32 timing) =20 if (priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type =3D=3D DW_MCI_TYPE_ARTPEC8) mci_writel(host, CLKSEL64, clksel); else @@ -223,6 +244,8 @@ static int dw_mci_exynos_resume_noirq(struct device *de= v) =20 if (priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type =3D=3D DW_MCI_TYPE_ARTPEC8) clksel =3D mci_readl(host, CLKSEL64); else @@ -231,6 +254,8 @@ static int dw_mci_exynos_resume_noirq(struct device *de= v) if (clksel & SDMMC_CLKSEL_WAKEUP_INT) { if (priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type =3D=3D DW_MCI_TYPE_ARTPEC8) mci_writel(host, CLKSEL64, clksel); else @@ -410,6 +435,8 @@ static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mc= i *host) =20 if (priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type =3D=3D DW_MCI_TYPE_ARTPEC8) return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64)); else @@ -423,6 +450,8 @@ static inline void dw_mci_exynos_set_clksmpl(struct dw_= mci *host, u8 sample) =20 if (priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type =3D=3D DW_MCI_TYPE_ARTPEC8) clksel =3D mci_readl(host, CLKSEL64); else @@ -430,6 +459,8 @@ static inline void dw_mci_exynos_set_clksmpl(struct dw_= mci *host, u8 sample) clksel =3D SDMMC_CLKSEL_UP_SAMPLE(clksel, sample); if (priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type =3D=3D DW_MCI_TYPE_ARTPEC8) mci_writel(host, CLKSEL64, clksel); else @@ -444,6 +475,8 @@ static inline u8 dw_mci_exynos_move_next_clksmpl(struct= dw_mci *host) =20 if (priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type =3D=3D DW_MCI_TYPE_ARTPEC8) clksel =3D mci_readl(host, CLKSEL64); else @@ -454,6 +487,8 @@ static inline u8 dw_mci_exynos_move_next_clksmpl(struct= dw_mci *host) =20 if (priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type =3D=3D DW_MCI_TYPE_ARTPEC8) mci_writel(host, CLKSEL64, clksel); else @@ -633,6 +668,12 @@ static const struct of_device_id dw_mci_exynos_match[]= =3D { .data =3D &exynos_drv_data, }, { .compatible =3D "samsung,exynos7-dw-mshc-smu", .data =3D &exynos_drv_data, }, + /* XXX: more SoCs probably have the same quirk, + the compatible should be something more generic */ + { .compatible =3D "samsung,exynos7885-dw-mshc", + .data =3D &exynos_drv_data, }, + { .compatible =3D "samsung,exynos7885-dw-mshc-smu", + .data =3D &exynos_drv_data, }, { .compatible =3D "axis,artpec8-dw-mshc", .data =3D &artpec_drv_data, }, {}, diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index 581614196..9fe816c61 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -2575,6 +2575,119 @@ static void dw_mci_pull_data64(struct dw_mci *host,= void *buf, int cnt) } } =20 +/* + Some dw_mmc devices have 64-bit FIFOs, but expect them to be + accessed using two 32-bit accesses. If such controller is used + with a 64-bit kernel, this has to be done explicitly. + + XXX: Is this issue specific to Exynos7? +*/ + +static inline uint64_t mci_fifo_readq_32(void __iomem *addr) +{ + uint64_t ans; + uint32_t proxy[2]; + + proxy[0] =3D mci_fifo_readl(addr); + proxy[1] =3D mci_fifo_readl(addr+4); + memcpy(&ans, proxy, 8); + return ans; +} + +static inline void mci_fifo_writeq_32(void __iomem *addr, uint64_t value) +{ + uint32_t proxy[2]; + + memcpy(proxy, &value, 8); + mci_fifo_writel(addr, proxy[0]); + mci_fifo_writel(addr+4, proxy[1]); +} + +static void dw_mci_push_data64_32(struct dw_mci *host, void *buf, int cnt) +{ + struct mmc_data *data =3D host->data; + int init_cnt =3D cnt; + + /* try and push anything in the part_buf */ + if (unlikely(host->part_buf_count)) { + int len =3D dw_mci_push_part_bytes(host, buf, cnt); + + buf +=3D len; + cnt -=3D len; + + if (host->part_buf_count =3D=3D 8) { + mci_fifo_writeq_32(host->fifo_reg, host->part_buf); + host->part_buf_count =3D 0; + } + } +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS + if (unlikely((unsigned long)buf & 0x7)) { + while (cnt >=3D 8) { + u64 aligned_buf[16]; + int len =3D min(cnt & -8, (int)sizeof(aligned_buf)); + int items =3D len >> 3; + int i; + /* memcpy from input buffer into aligned buffer */ + memcpy(aligned_buf, buf, len); + buf +=3D len; + cnt -=3D len; + /* push data from aligned buffer into fifo */ + for (i =3D 0; i < items; ++i) + mci_fifo_writeq_32(host->fifo_reg, aligned_buf[i]); + } + } else +#endif + { + u64 *pdata =3D buf; + + for (; cnt >=3D 8; cnt -=3D 8) + mci_fifo_writeq_32(host->fifo_reg, *pdata++); + buf =3D pdata; + } + /* put anything remaining in the part_buf */ + if (cnt) { + dw_mci_set_part_bytes(host, buf, cnt); + /* Push data if we have reached the expected data length */ + if ((data->bytes_xfered + init_cnt) =3D=3D + (data->blksz * data->blocks)) + mci_fifo_writeq_32(host->fifo_reg, host->part_buf); + } +} + +static void dw_mci_pull_data64_32(struct dw_mci *host, void *buf, int cnt) +{ +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS + if (unlikely((unsigned long)buf & 0x7)) { + while (cnt >=3D 8) { + /* pull data from fifo into aligned buffer */ + u64 aligned_buf[16]; + int len =3D min(cnt & -8, (int)sizeof(aligned_buf)); + int items =3D len >> 3; + int i; + + for (i =3D 0; i < items; ++i) + aligned_buf[i] =3D mci_fifo_readq_32(host->fifo_reg); + + /* memcpy from aligned buffer into output buffer */ + memcpy(buf, aligned_buf, len); + buf +=3D len; + cnt -=3D len; + } + } else +#endif + { + u64 *pdata =3D buf; + + for (; cnt >=3D 8; cnt -=3D 8) + *pdata++ =3D mci_fifo_readq_32(host->fifo_reg); + buf =3D pdata; + } + if (cnt) { + host->part_buf =3D mci_fifo_readq_32(host->fifo_reg); + dw_mci_pull_final_bytes(host, buf, cnt); + } +} + static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) { int len; @@ -3367,8 +3480,13 @@ int dw_mci_probe(struct dw_mci *host) width =3D 16; host->data_shift =3D 1; } else if (i =3D=3D 2) { - host->push_data =3D dw_mci_push_data64; - host->pull_data =3D dw_mci_pull_data64; + if ((host->quirks & DW_MMC_QUIRK_FIFO64_32)) { + host->push_data =3D dw_mci_push_data64_32; + host->pull_data =3D dw_mci_pull_data64_32; + } else { + host->push_data =3D dw_mci_push_data64; + host->pull_data =3D dw_mci_pull_data64; + } width =3D 64; host->data_shift =3D 3; } else { diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h index 4ed81f94f..edd642b92 100644 --- a/drivers/mmc/host/dw_mmc.h +++ b/drivers/mmc/host/dw_mmc.h @@ -280,6 +280,8 @@ struct dw_mci_board { =20 /* Support for longer data read timeout */ #define DW_MMC_QUIRK_EXTENDED_TMOUT BIT(0) +/* Force 32-bit access to the FIFO */ +#define DW_MMC_QUIRK_FIFO64_32 BIT(1) =20 #define DW_MMC_240A 0x240a #define DW_MMC_280A 0x280a --=20 2.38.3