From nobody Wed Feb 11 17:21:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E10FC6FA99 for ; Sun, 12 Mar 2023 17:03:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230448AbjCLRDJ (ORCPT ); Sun, 12 Mar 2023 13:03:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50004 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231224AbjCLRDA (ORCPT ); Sun, 12 Mar 2023 13:03:00 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2CF2339BBC for ; Sun, 12 Mar 2023 10:02:44 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id d36so12842131lfv.8 for ; Sun, 12 Mar 2023 10:02:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1678640562; h=cc:to:subject:date:from:in-reply-to:message-id:from:to:cc:subject :date:message-id:reply-to; bh=bMzb4+f+2BylShTzIH+kD9h/2l/yJ2pk3VVMD+904ak=; b=UcgQEUTeekUE+yO0Pfm+bm9izAiSVibcvIffL015exUwnHDJuG8iZEHRC3h2DRu4A8 j6rMpg6coJh4Z8X1Dj/PxIdUxERGROjPj959rb9YoDLajnVivD5BCvErNAS4Bjf/zgyq HElDaIT9e3SNBbFFYtIAXh19eeBdPY7qU/vBaHAiIfq03AhSHyzkiD8TZcckk/nsr5jp 0/fWjXXg2p8+Uk160ywZD/cwDQfZS+o9Bc2Xw2xoWaVAbie9eDuoXrGz8NxXbyI+JRDN W1ZeGeLyx1sVMXgB1PLHnAkJXJQaVrM1RVzqkNghlM2ngaH/mbOcNzaAfOMfUw5feOif o3Gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678640562; h=cc:to:subject:date:from:in-reply-to:message-id:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=bMzb4+f+2BylShTzIH+kD9h/2l/yJ2pk3VVMD+904ak=; b=w9eWGQCy7VnHHZ7wSvIcRwLAUwXBYLYtfykn6eDYOfNXMThqm3z2f4V9ev2b49DqHe rxs2oW0nM97EVx8xU++M8nK8WAOfakzG7DOSUKhm04VWDtoIQC68XbwvQijUtUR2Q8si XZ1JkwcGNMwjV9uBQ4ufMacdBD7tdpNCternRKgNHDC9uFke9c4jMs2KBUuUifv2Hl8m Q1r/w/7qTiQn4zSwgViI+1VKxEpo4cRJVxOFNDBtl0/xSCi0t5wyOAQip3Rsm3Gy5hUw Ckacj2z+JMK55mN2EY8fTChIq1X9piUrc3JNa2CSVQZCf8qawFnumD8t+6zvGoZEmBcY ds1Q== X-Gm-Message-State: AO0yUKUX8/BxOnxmVLYYOb+cyxh6Mk9aG9vTggRJNBFMA7LxLa6utkAH TcMOQeyf3bLmynX4PT+0cmLeqFYpnOdRUah6 X-Google-Smtp-Source: AK7set9ZlTH17G0FnW+z13Pb1s3HaUJEmtKLrWEW5BIxE79NrmbvApt2Nmyr1n9kVAWtfq5kdkDqkA== X-Received: by 2002:ac2:563a:0:b0:4de:290:1c0a with SMTP id b26-20020ac2563a000000b004de02901c0amr9292769lff.57.1678640562189; Sun, 12 Mar 2023 10:02:42 -0700 (PDT) Received: from 0001-dt-bindings-exynos-dw-mshc-common-add-exynos78xx-var.patch (46-138-144-249.dynamic.spd-mgts.ru. [46.138.144.249]) by smtp.gmail.com with ESMTPSA id b9-20020ac25e89000000b0047f7722b73csm693942lfq.142.2023.03.12.10.02.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Mar 2023 10:02:41 -0700 (PDT) Message-Id: <1678640497.9030156-1-sleirsgoevy@gmail.com> In-Reply-To: <1678640497.9030156-0-sleirsgoevy@gmail.com> From: Sergey Lisov Date: Sun, 12 Mar 2023 19:59:29 +0300 Subject: [PATCH v4 1/3] dt-bindings: exynos-dw-mshc-common: add exynos78xx variants To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Alim Akhtar , Jaehoon Chung Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Some Samsung Exynos boards using the arm64 architecture have DW MMC controllers configured for a 32-bit data bus but a 64-bit FIFO. On these systems the 64-bit FIFO registers must be accessed in two 32-bit halves. Add two new compatible strings, "samsung,exynos78xx-dw-mshc" and "samsung,exynos78xx-dw-mshc-smu" respectively, to denote exynos78xx boards that need this quirk. But it's very possible that all "samsung,exynos7-dw-mshc" boards are actually affected. --- .../devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.y= aml b/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml index fdaa18481..a72a67792 100644 --- a/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml +++ b/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml @@ -22,6 +22,8 @@ properties: - samsung,exynos5420-dw-mshc-smu - samsung,exynos7-dw-mshc - samsung,exynos7-dw-mshc-smu + - samsung,exynos78xx-dw-mshc + - samsung,exynos78xx-dw-mshc-smu - axis,artpec8-dw-mshc =20 reg: --=20 2.38.3 From nobody Wed Feb 11 17:21:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F117C6FD19 for ; Sun, 12 Mar 2023 17:03:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231233AbjCLRDU (ORCPT ); Sun, 12 Mar 2023 13:03:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50164 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229983AbjCLRDL (ORCPT ); Sun, 12 Mar 2023 13:03:11 -0400 Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9781F136C7 for ; Sun, 12 Mar 2023 10:03:09 -0700 (PDT) Received: by mail-lj1-x22e.google.com with SMTP id b10so10350134ljr.0 for ; Sun, 12 Mar 2023 10:03:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1678640587; h=cc:to:subject:date:from:in-reply-to:message-id:from:to:cc:subject :date:message-id:reply-to; bh=yNccjh9ehO5GzEa2MK08HfZDjH6EdpZB9/Uqslpa9j8=; b=kqxQc/lcfo4O3IVrgdqCwnLQ5D9feVCpykVHIU24WhenM+Qth3A/LcFZ62Y9ObaAE/ /l4+V3B5Qia7SHqTU+onjX2c4spNndhX45Q85vRSaAk2eaBMM/wygg2xrVN9+ydkslcc 4xxuYHayRBE54rpDftHLSzST4lAWUuyzyx8oLqpZ1LUD32itTU8EzOzJVe5tshwSIb+d qMcW0KMD9pi96gz0qVnB42T0ZarjOCLJV4s+phGdTrGY9cTs+Hl+7/rrK2o2BG0u04HT yu2lAH9XI8Cu4m8bTPRrTqIjw2xKsZEiAx+hsrS8YB8voocwj8v6pEwNQ/8jLabEumpX pZGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678640587; h=cc:to:subject:date:from:in-reply-to:message-id:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=yNccjh9ehO5GzEa2MK08HfZDjH6EdpZB9/Uqslpa9j8=; b=hRrt7P69RVmeatTMMX4H05wDiJC20sLFvL6WfYYFTX5fSpm/hmTPrdC4e+vvB2Zt8V oq0QghkGOVs8HrDzSs7m+clfjHo+7WLgP5eaB/wUZDBm3yI4N24XX1M7DOiqz0WQ6doz nJcptCbacAJxW5+ljsEyv4R7tsPWtdgNkSNwNkCsxAtXwFRvvR9zJBT3pHB9W4xK8Uey pWGVV3DTouYiKaBRyKD+dF2M+jHD/jVDnqaIDSi5RH0ritTsgQ0jEMHwWc2ElogogN2u FsBPWkth0M3aPw6p/mtVe7zJ7fupY+yOAWoyVdH8xjY3t5JCRWZNOlt3bgGoBuQQBL/1 lEig== X-Gm-Message-State: AO0yUKVBVAEZeCt0ZV3iL5I7yF9TwJ3H4OdMFzpGDCWEjcoo0z0PBnsx DWugpmKmrk1FSF3WGRoNoxBxZ4rqZP0wTdud X-Google-Smtp-Source: AK7set8BOLzpIW3pOLVKY2LIne3PACEnL5Yfe+3qT6YltcHnreYWCJZUEWsddE1w9TwwulfaHa9GLg== X-Received: by 2002:a2e:a586:0:b0:298:39fa:b04d with SMTP id m6-20020a2ea586000000b0029839fab04dmr11384348ljp.33.1678640587405; Sun, 12 Mar 2023 10:03:07 -0700 (PDT) Received: from 0002-arm64-dts-exynos-fix-wrong-mmc-compatible-in-exynos7.patch (46-138-144-249.dynamic.spd-mgts.ru. [46.138.144.249]) by smtp.gmail.com with ESMTPSA id r2-20020a2e94c2000000b0029335c12997sm704396ljh.58.2023.03.12.10.03.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Mar 2023 10:03:07 -0700 (PDT) Message-Id: <1678640497.9030156-2-sleirsgoevy@gmail.com> In-Reply-To: <1678640497.9030156-0-sleirsgoevy@gmail.com> From: Sergey Lisov Date: Sun, 12 Mar 2023 19:59:29 +0300 Subject: [PATCH v4 2/3] arm64: dts: exynos: fix wrong mmc compatible in exynos7885.dtsi To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Alim Akhtar , Jaehoon Chung Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This DW-MMC variant is not actually compatible with "samsung,exynos7-dw-mshc-smu", and requires an additional quirk to handle very short data transfers. Update the compatible string to "samsung,exynos78xx-dw-mshc-smu" to reflect this fact. --- arch/arm64/boot/dts/exynos/exynos7885.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/exynos/exynos7885.dtsi b/arch/arm64/boot/d= ts/exynos/exynos7885.dtsi index 23c2e0bb0..4b94ac9da 100644 --- a/arch/arm64/boot/dts/exynos/exynos7885.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7885.dtsi @@ -294,7 +294,7 @@ pmu_system_controller: system-controller@11c80000 { }; =20 mmc_0: mmc@13500000 { - compatible =3D "samsung,exynos7-dw-mshc-smu"; + compatible =3D "samsung,exynos78xx-dw-mshc-smu"; reg =3D <0x13500000 0x2000>; interrupts =3D ; #address-cells =3D <1>; --=20 2.38.3 From nobody Wed Feb 11 17:21:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B263BC6FD1C for ; Sun, 12 Mar 2023 17:03:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229742AbjCLRDt (ORCPT ); Sun, 12 Mar 2023 13:03:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51312 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229783AbjCLRDp (ORCPT ); Sun, 12 Mar 2023 13:03:45 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B4DF21E5DF for ; Sun, 12 Mar 2023 10:03:37 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id r27so12829376lfe.10 for ; Sun, 12 Mar 2023 10:03:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1678640617; h=cc:to:subject:date:from:in-reply-to:message-id:from:to:cc:subject :date:message-id:reply-to; bh=cPk/h023+CvWv4LEM2Nr7aafr5OCIjbP3l84sbGJHt4=; b=A6vDBsQAlDkhFoEtH91yFDEb6IKw1EtV2xIWs040eP+UPWWKy5CWcvPLM6sw9gQHaG lmaemtc5jEhbL5s3JYct0A75JiDKp7PsPr1oZRqU8yme/jZZrnx772Prbw+T1nPr9Fna 2ChXIW9GqR7tXSwjlM8HwWfwebHVGPeycEUKo0+Dqvc/d1SQ+FgbD1SnTJmJ9GetC2I6 x+HtUXZqgDA7bAdXjELpWCl61vuex/sKro5zOED4g2G0NKCPQzSR3r1vd255ctbo4V/7 JiGOYwuIodqGxFCGLvW7JmotxL+I5D6r7hjot6VXyXMuRCpbzvkRaN/uchulItUDIjH2 srMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678640617; h=cc:to:subject:date:from:in-reply-to:message-id:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=cPk/h023+CvWv4LEM2Nr7aafr5OCIjbP3l84sbGJHt4=; b=morfWN9tgdLRBrOQYTBUwrGhDUWGblF4MrmzeCPa1mMC1tsljigxk+2dK9ckXZq5wc mtfAYOe94TCj/1YD9KTLSzdEZq3aa2sV6y99rirhMScxU+wAqct8jRPwKV5Qf1g3DTbM aPHoGo39drjTRsRGB/eFsfQfTFZ2y9SzkFaJuyp904jYVZ2gf+/sX/Ol5xpJs5VX7jil PXY/GqDL5XqzI5XEmVal0h2+KfvAUonrkBiZ/mDG8Ic1jJRjl7lO2QCfmqOhXqkdoAu1 j7fj5iEDdWJ9uoR4rrSGl2ucZKJf9y572+idfDJu09/8AnLIQRCJj4nqL0fmR4iAtngw 7r7Q== X-Gm-Message-State: AO0yUKUU31DAoQ/D5F3UHEueCnDwRuoo8HSjS3ubBpusxE4vLcGRdHqJ SXtCzH0QRZpwzHcFIZw4Zw0AOUNibQUyJnoQ X-Google-Smtp-Source: AK7set+eMuzDYy1jzQOMtR+RzW191Hg1SUQRu74FMVNboAt6LjF6gNzo/YnlCThO6SWPZs0yRRCIkw== X-Received: by 2002:a19:ae13:0:b0:4e1:13fa:bf07 with SMTP id f19-20020a19ae13000000b004e113fabf07mr9633714lfc.43.1678640616940; Sun, 12 Mar 2023 10:03:36 -0700 (PDT) Received: from 0003-mmc-dw_mmc-add-an-option-to-force-32-bit-access-to-6.patch (46-138-144-249.dynamic.spd-mgts.ru. [46.138.144.249]) by smtp.gmail.com with ESMTPSA id w6-20020a05651203c600b004cc7acfbd2bsm703725lfp.287.2023.03.12.10.03.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Mar 2023 10:03:36 -0700 (PDT) Message-Id: <1678640497.9030156-3-sleirsgoevy@gmail.com> In-Reply-To: <1678640497.9030156-0-sleirsgoevy@gmail.com> From: Sergey Lisov Date: Sun, 12 Mar 2023 19:59:30 +0300 Subject: [PATCH v4 3/3] mmc: dw_mmc: add an option to force 32-bit access to 64-bit FIFO To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Alim Akhtar , Jaehoon Chung Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Some Samsung Exynos boards using the arm64 architecture have DW MMC controllers configured for a 32-bit data bus but a 64-bit FIFO. On these systems the 64-bit FIFO registers must be accessed in two 32-bit halves. --- drivers/mmc/host/dw_mmc-exynos.c | 41 ++++++++++- drivers/mmc/host/dw_mmc.c | 122 ++++++++++++++++++++++++++++++- drivers/mmc/host/dw_mmc.h | 2 + 3 files changed, 162 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exy= nos.c index 9f20ac524..768774f22 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c @@ -28,6 +28,8 @@ enum dw_mci_exynos_type { DW_MCI_TYPE_EXYNOS5420_SMU, DW_MCI_TYPE_EXYNOS7, DW_MCI_TYPE_EXYNOS7_SMU, + DW_MCI_TYPE_EXYNOS78XX, + DW_MCI_TYPE_EXYNOS78XX_SMU, DW_MCI_TYPE_ARTPEC8, }; =20 @@ -70,6 +72,12 @@ static struct dw_mci_exynos_compatible { }, { .compatible =3D "samsung,exynos7-dw-mshc-smu", .ctrl_type =3D DW_MCI_TYPE_EXYNOS7_SMU, + }, { + .compatible =3D "samsung,exynos78xx-dw-mshc", + .ctrl_type =3D DW_MCI_TYPE_EXYNOS78XX, + }, { + .compatible =3D "samsung,exynos78xx-dw-mshc-smu", + .ctrl_type =3D DW_MCI_TYPE_EXYNOS78XX_SMU, }, { .compatible =3D "axis,artpec8-dw-mshc", .ctrl_type =3D DW_MCI_TYPE_ARTPEC8, @@ -86,6 +94,8 @@ static inline u8 dw_mci_exynos_get_ciu_div(struct dw_mci = *host) return EXYNOS4210_FIXED_CIU_CLK_DIV; else if (priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type =3D=3D DW_MCI_TYPE_ARTPEC8) return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL64)) + 1; else @@ -101,7 +111,8 @@ static void dw_mci_exynos_config_smu(struct dw_mci *hos= t) * set for non-ecryption mode at this time. */ if (priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS5420_SMU || - priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7_SMU) { + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX_SMU) { mci_writel(host, MPSBEGIN0, 0); mci_writel(host, MPSEND0, SDMMC_ENDING_SEC_NR_MAX); mci_writel(host, MPSCTRL0, SDMMC_MPSCTRL_SECURE_WRITE_BIT | @@ -127,6 +138,12 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host) DQS_CTRL_GET_RD_DELAY(priv->saved_strobe_ctrl); } =20 + if (priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX_SMU) { + /* Quirk needed for certain Exynos SoCs */ + host->quirks |=3D DW_MMC_QUIRK_FIFO64_32; + } + if (priv->ctrl_type =3D=3D DW_MCI_TYPE_ARTPEC8) { /* Quirk needed for the ARTPEC-8 SoC */ host->quirks |=3D DW_MMC_QUIRK_EXTENDED_TMOUT; @@ -144,6 +161,8 @@ static void dw_mci_exynos_set_clksel_timing(struct dw_m= ci *host, u32 timing) =20 if (priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type =3D=3D DW_MCI_TYPE_ARTPEC8) clksel =3D mci_readl(host, CLKSEL64); else @@ -153,6 +172,8 @@ static void dw_mci_exynos_set_clksel_timing(struct dw_m= ci *host, u32 timing) =20 if (priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type =3D=3D DW_MCI_TYPE_ARTPEC8) mci_writel(host, CLKSEL64, clksel); else @@ -223,6 +244,8 @@ static int dw_mci_exynos_resume_noirq(struct device *de= v) =20 if (priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type =3D=3D DW_MCI_TYPE_ARTPEC8) clksel =3D mci_readl(host, CLKSEL64); else @@ -231,6 +254,8 @@ static int dw_mci_exynos_resume_noirq(struct device *de= v) if (clksel & SDMMC_CLKSEL_WAKEUP_INT) { if (priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type =3D=3D DW_MCI_TYPE_ARTPEC8) mci_writel(host, CLKSEL64, clksel); else @@ -410,6 +435,8 @@ static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mc= i *host) =20 if (priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type =3D=3D DW_MCI_TYPE_ARTPEC8) return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64)); else @@ -423,6 +450,8 @@ static inline void dw_mci_exynos_set_clksmpl(struct dw_= mci *host, u8 sample) =20 if (priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type =3D=3D DW_MCI_TYPE_ARTPEC8) clksel =3D mci_readl(host, CLKSEL64); else @@ -430,6 +459,8 @@ static inline void dw_mci_exynos_set_clksmpl(struct dw_= mci *host, u8 sample) clksel =3D SDMMC_CLKSEL_UP_SAMPLE(clksel, sample); if (priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type =3D=3D DW_MCI_TYPE_ARTPEC8) mci_writel(host, CLKSEL64, clksel); else @@ -444,6 +475,8 @@ static inline u8 dw_mci_exynos_move_next_clksmpl(struct= dw_mci *host) =20 if (priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type =3D=3D DW_MCI_TYPE_ARTPEC8) clksel =3D mci_readl(host, CLKSEL64); else @@ -454,6 +487,8 @@ static inline u8 dw_mci_exynos_move_next_clksmpl(struct= dw_mci *host) =20 if (priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type =3D=3D DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type =3D=3D DW_MCI_TYPE_ARTPEC8) mci_writel(host, CLKSEL64, clksel); else @@ -633,6 +668,10 @@ static const struct of_device_id dw_mci_exynos_match[]= =3D { .data =3D &exynos_drv_data, }, { .compatible =3D "samsung,exynos7-dw-mshc-smu", .data =3D &exynos_drv_data, }, + { .compatible =3D "samsung,exynos78xx-dw-mshc", + .data =3D &exynos_drv_data, }, + { .compatible =3D "samsung,exynos78xx-dw-mshc-smu", + .data =3D &exynos_drv_data, }, { .compatible =3D "axis,artpec8-dw-mshc", .data =3D &artpec_drv_data, }, {}, diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index 581614196..9fe816c61 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -2575,6 +2575,119 @@ static void dw_mci_pull_data64(struct dw_mci *host,= void *buf, int cnt) } } =20 +/* + Some dw_mmc devices have 64-bit FIFOs, but expect them to be + accessed using two 32-bit accesses. If such controller is used + with a 64-bit kernel, this has to be done explicitly. + + XXX: Is this issue specific to Exynos7? +*/ + +static inline uint64_t mci_fifo_readq_32(void __iomem *addr) +{ + uint64_t ans; + uint32_t proxy[2]; + + proxy[0] =3D mci_fifo_readl(addr); + proxy[1] =3D mci_fifo_readl(addr+4); + memcpy(&ans, proxy, 8); + return ans; +} + +static inline void mci_fifo_writeq_32(void __iomem *addr, uint64_t value) +{ + uint32_t proxy[2]; + + memcpy(proxy, &value, 8); + mci_fifo_writel(addr, proxy[0]); + mci_fifo_writel(addr+4, proxy[1]); +} + +static void dw_mci_push_data64_32(struct dw_mci *host, void *buf, int cnt) +{ + struct mmc_data *data =3D host->data; + int init_cnt =3D cnt; + + /* try and push anything in the part_buf */ + if (unlikely(host->part_buf_count)) { + int len =3D dw_mci_push_part_bytes(host, buf, cnt); + + buf +=3D len; + cnt -=3D len; + + if (host->part_buf_count =3D=3D 8) { + mci_fifo_writeq_32(host->fifo_reg, host->part_buf); + host->part_buf_count =3D 0; + } + } +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS + if (unlikely((unsigned long)buf & 0x7)) { + while (cnt >=3D 8) { + u64 aligned_buf[16]; + int len =3D min(cnt & -8, (int)sizeof(aligned_buf)); + int items =3D len >> 3; + int i; + /* memcpy from input buffer into aligned buffer */ + memcpy(aligned_buf, buf, len); + buf +=3D len; + cnt -=3D len; + /* push data from aligned buffer into fifo */ + for (i =3D 0; i < items; ++i) + mci_fifo_writeq_32(host->fifo_reg, aligned_buf[i]); + } + } else +#endif + { + u64 *pdata =3D buf; + + for (; cnt >=3D 8; cnt -=3D 8) + mci_fifo_writeq_32(host->fifo_reg, *pdata++); + buf =3D pdata; + } + /* put anything remaining in the part_buf */ + if (cnt) { + dw_mci_set_part_bytes(host, buf, cnt); + /* Push data if we have reached the expected data length */ + if ((data->bytes_xfered + init_cnt) =3D=3D + (data->blksz * data->blocks)) + mci_fifo_writeq_32(host->fifo_reg, host->part_buf); + } +} + +static void dw_mci_pull_data64_32(struct dw_mci *host, void *buf, int cnt) +{ +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS + if (unlikely((unsigned long)buf & 0x7)) { + while (cnt >=3D 8) { + /* pull data from fifo into aligned buffer */ + u64 aligned_buf[16]; + int len =3D min(cnt & -8, (int)sizeof(aligned_buf)); + int items =3D len >> 3; + int i; + + for (i =3D 0; i < items; ++i) + aligned_buf[i] =3D mci_fifo_readq_32(host->fifo_reg); + + /* memcpy from aligned buffer into output buffer */ + memcpy(buf, aligned_buf, len); + buf +=3D len; + cnt -=3D len; + } + } else +#endif + { + u64 *pdata =3D buf; + + for (; cnt >=3D 8; cnt -=3D 8) + *pdata++ =3D mci_fifo_readq_32(host->fifo_reg); + buf =3D pdata; + } + if (cnt) { + host->part_buf =3D mci_fifo_readq_32(host->fifo_reg); + dw_mci_pull_final_bytes(host, buf, cnt); + } +} + static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) { int len; @@ -3367,8 +3480,13 @@ int dw_mci_probe(struct dw_mci *host) width =3D 16; host->data_shift =3D 1; } else if (i =3D=3D 2) { - host->push_data =3D dw_mci_push_data64; - host->pull_data =3D dw_mci_pull_data64; + if ((host->quirks & DW_MMC_QUIRK_FIFO64_32)) { + host->push_data =3D dw_mci_push_data64_32; + host->pull_data =3D dw_mci_pull_data64_32; + } else { + host->push_data =3D dw_mci_push_data64; + host->pull_data =3D dw_mci_pull_data64; + } width =3D 64; host->data_shift =3D 3; } else { diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h index 4ed81f94f..edd642b92 100644 --- a/drivers/mmc/host/dw_mmc.h +++ b/drivers/mmc/host/dw_mmc.h @@ -280,6 +280,8 @@ struct dw_mci_board { =20 /* Support for longer data read timeout */ #define DW_MMC_QUIRK_EXTENDED_TMOUT BIT(0) +/* Force 32-bit access to the FIFO */ +#define DW_MMC_QUIRK_FIFO64_32 BIT(1) =20 #define DW_MMC_240A 0x240a #define DW_MMC_280A 0x280a --=20 2.38.3