From nobody Wed Feb 11 17:21:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 279AAC6FD1C for ; Sat, 11 Mar 2023 18:22:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229469AbjCKSWd (ORCPT ); Sat, 11 Mar 2023 13:22:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36380 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229809AbjCKSW3 (ORCPT ); Sat, 11 Mar 2023 13:22:29 -0500 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E179C59E7C for ; Sat, 11 Mar 2023 10:21:48 -0800 (PST) Received: by mail-lf1-x135.google.com with SMTP id bi9so10767552lfb.2 for ; Sat, 11 Mar 2023 10:21:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1678558903; h=cc:to:subject:date:from:in-reply-to:message-id:from:to:cc:subject :date:message-id:reply-to; bh=zgZZFa9GT3KgzmxYSLg5VRVJ2/WUIFA9QnWnNW5nD4w=; b=cv8Tww7Hl739LopzBthOGhZy4VlB2lYgMNEJ49Af7R8DnMDgc3eQyxpawmtQGGbnJe 25M5PIR2XqPtsEqsMskeyVnSx6yY2J/bMmEO7Ur24ZGeUPehvNgDWHnrcaKCBnG1sc1O iMwgKaDW1uJuSG7fArGJ+u2X4RWggw5RzIy81LlKRvNjIBC+2S46UpmqZv6WywqWP1Wu nmMt1sS6+skpibAwG5HveoUvKXHXhXIjh0+6ditULRjkO68/MCxHUN+ASOm++biOljZ9 r8+4Pd9a9jfXKPpZ39ihqiP9PQpc55/bC10Q3lzP7xHTRd2vzEz0dvEvwz24rgMYpB+h w2Sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678558903; h=cc:to:subject:date:from:in-reply-to:message-id:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=zgZZFa9GT3KgzmxYSLg5VRVJ2/WUIFA9QnWnNW5nD4w=; b=qpnGbVC3qUQmc8IwHC97KbnvZazWW9k/1eKvj2VOQDoWOO1yeC2kIg/U6z4iEl4c5m xX5dsLFALqHFIQpolp42KZRNVcWfFBM8MMhMiM7BtY/U4n9XCurTiyMaPBXt1O55lMD3 WuLuG13CpMhJeIGJRd2HIN8e+ouu3F1oElWGkk3uOzktnFe8nzrVM9kS1R2rmzrmoADw cjIZlpoaeF6oQ/c7wCgmr1kkkneCL58oP9ZM5GmWMJvtUTDz87NJBQIR1Rpo+oPYCKFP 75w6rwN97b5xudonLeqmLfmP4Ld1rklT5gn+vscK5jDfGNdYkKvoXiyqAHV8Sl7SWTJe lNVw== X-Gm-Message-State: AO0yUKU5yzDbDx2oPFyttxb8Foe8LYUBQxY7XDZsP2g1Xn9ZrIHD9cCt sxa/es/tW+tIqn1SqyLhsQp1iZb9uMDRt02L1rc= X-Google-Smtp-Source: AK7set+IdgFrYxey9LQTQHJF5c9vczy+XT0K28uYXRK0qnHbMOYdzDbTIGUYhAnWf+Id39ZczlRudA== X-Received: by 2002:a05:6512:24b:b0:4e1:46e9:ec3e with SMTP id b11-20020a056512024b00b004e146e9ec3emr8784984lfo.61.1678558903223; Sat, 11 Mar 2023 10:21:43 -0800 (PST) Received: from 0001-dt-bindings-synopsys-dw-mshc-common-add-fifo-access-.patch (46-138-144-249.dynamic.spd-mgts.ru. [46.138.144.249]) by smtp.gmail.com with ESMTPSA id w25-20020ac25999000000b004e811e3554dsm386680lfn.185.2023.03.11.10.21.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Mar 2023 10:21:43 -0800 (PST) Message-Id: <1678558770.495747-1-sleirsgoevy@gmail.com> In-Reply-To: <1678558770.495747-0-sleirsgoevy@gmail.com> From: Sergey Lisov Date: Sat, 11 Mar 2023 21:15:37 +0300 Subject: [PATCH v2 1/2] dt-bindings: synopsys-dw-mshc-common: add "fifo-access-32bit" property To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Jaehoon Chung Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Some Samsung Exynos boards using the arm64 architecture have DW MMC controllers configured for a 32-bit data bus but a 64-bit FIFO. On these systems the 64-bit FIFO registers must be accessed in two 32-bit halves. --- .../devicetree/bindings/mmc/synopsys-dw-mshc-common.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc-common.= yaml b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc-common.yaml index 8dfad89c7..d025b38ca 100644 --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc-common.yaml +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc-common.yaml @@ -57,6 +57,13 @@ properties: force fifo watermark setting accordingly. $ref: /schemas/types.yaml#/definitions/flag =20 + fifo-access-32bit: + description: + Specifies that this device requires accesses to its 64-bit registers + to be done as pairs of 32-bit accesses, even on architectures where + readq is available. + $ref: /schemas/types.yaml#/definitions/flag + dmas: maxItems: 1 =20 --=20 2.38.3 From nobody Wed Feb 11 17:21:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35AD1C61DA4 for ; Sat, 11 Mar 2023 18:22:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229983AbjCKSWt (ORCPT ); Sat, 11 Mar 2023 13:22:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36944 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230445AbjCKSWm (ORCPT ); Sat, 11 Mar 2023 13:22:42 -0500 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C4616C19F for ; Sat, 11 Mar 2023 10:22:13 -0800 (PST) Received: by mail-lf1-x135.google.com with SMTP id g17so10769977lfv.4 for ; Sat, 11 Mar 2023 10:22:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1678558931; h=cc:to:subject:date:from:in-reply-to:message-id:from:to:cc:subject :date:message-id:reply-to; bh=JmnRhaQGnYcC7TxoQ5v3x/8cn+va4CZCsQk0t4OobFo=; b=WYCZcdn0o0WvwD3HVutVeCwLIC5TUcMr475caURi5mX9VtFdkb/7ywkOGr9ngPIkse ez/++hIogO8vn26XGNW4M+Uyzv+Pf2xDC+bHTvnAI9diFrg2Qj6Y4VTJ1Hc2kunK54dU YFuw/EWVBA7XJozExD2qRI1iDb9biT/vf6L58eGy4AI4UQBBwfjCpslmRG1F/9rhJ1uA G+2vJipFsfjSvdUzakLrS/JDaYXbkRYOfa5a/Ti33cV+S+V8bVzmZ4NnEOEw1PJDaGWd WTbF2dSb05zW+qubeJijiwDQ7HBSPCpbqk3K0s/TNHuqmZz35o20juvxy+3giH/JWfMf BAxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678558931; h=cc:to:subject:date:from:in-reply-to:message-id:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=JmnRhaQGnYcC7TxoQ5v3x/8cn+va4CZCsQk0t4OobFo=; b=PCii1g0/5L+AgL7YlRk/UW+odLUDbcsSJwMKtwzyINTJHMyePf59jamGuK+JhLM6d2 AZBbyem7xbIm0G2KLh+n0qQJgJvPngIW3yxMKD3j1zikvELUHiQpNvsK3BnrujeVye9K HGppZDDkG3S8tz66zjKNv9A85nqKEOVCcXre1PQemjKyT2V2ljWypclGV7eZ64UDZrt1 nVk17bRybZ9JCaO5prpn+v5tWFg6hJQ09np6jmFtXuUYV7MsgWlksZ3zEVllggB1idDu NP6cA76yN4Y011zyiFwmhz4X1vc/DakbY9tWh804EM4fmbUlSoYLkUqHR8U8nfKm9Fgn Prbg== X-Gm-Message-State: AO0yUKVJptSSw0qlnhjoq8l9wqndNx1N9D4o/m24DL5un539loVWzEcN ZOVtDU+Jly5Fg+OkAGM3LqEiLgR75/KkdeI9 X-Google-Smtp-Source: AK7set8LyzNeCw6vXhwf+1sPhkOIFYIcvZx0d0Jj21TfrcZithQl3tW8pvtQBbnvFL3LVhavyu/rGg== X-Received: by 2002:ac2:4149:0:b0:4e8:3da6:485a with SMTP id c9-20020ac24149000000b004e83da6485amr443703lfi.68.1678558931254; Sat, 11 Mar 2023 10:22:11 -0800 (PST) Received: from 0002-mmc-dw_mmc-add-an-option-to-force-32-bit-access-to-6.patch (46-138-144-249.dynamic.spd-mgts.ru. [46.138.144.249]) by smtp.gmail.com with ESMTPSA id w25-20020a19c519000000b004dd6c325311sm384307lfe.248.2023.03.11.10.22.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Mar 2023 10:22:11 -0800 (PST) Message-Id: <1678558770.495747-2-sleirsgoevy@gmail.com> In-Reply-To: <1678558770.495747-0-sleirsgoevy@gmail.com> From: Sergey Lisov Date: Sat, 11 Mar 2023 21:15:38 +0300 Subject: [PATCH v2 2/2] mmc: dw_mmc: add an option to force 32-bit access to 64-bit FIFO To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Jaehoon Chung Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Some Samsung Exynos boards using the arm64 architecture have DW MMC controllers configured for a 32-bit data bus but a 64-bit FIFO. On these systems the 64-bit FIFO registers must be accessed in two 32-bit halves. --- drivers/mmc/host/dw_mmc.c | 125 +++++++++++++++++++++++++++++++++++++- drivers/mmc/host/dw_mmc.h | 2 + 2 files changed, 125 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index 581614196..eee430620 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -2575,6 +2575,119 @@ static void dw_mci_pull_data64(struct dw_mci *host,= void *buf, int cnt) } } =20 +/* + Some dw_mmc devices have 64-bit FIFOs, but expect them to be + accessed using two 32-bit accesses. If such controller is used + with a 64-bit kernel, this has to be done explicitly. + + XXX: Is this issue specific to Exynos7? +*/ + +static inline uint64_t mci_fifo_readq_32(void __iomem *addr) +{ + uint64_t ans; + uint32_t proxy[2]; + + proxy[0] =3D mci_fifo_readl(addr); + proxy[1] =3D mci_fifo_readl(addr+4); + memcpy(&ans, proxy, 8); + return ans; +} + +static inline void mci_fifo_writeq_32(void __iomem *addr, uint64_t value) +{ + uint32_t proxy[2]; + + memcpy(proxy, &value, 8); + mci_fifo_writel(addr, proxy[0]); + mci_fifo_writel(addr+4, proxy[1]); +} + +static void dw_mci_push_data64_32(struct dw_mci *host, void *buf, int cnt) +{ + struct mmc_data *data =3D host->data; + int init_cnt =3D cnt; + + /* try and push anything in the part_buf */ + if (unlikely(host->part_buf_count)) { + int len =3D dw_mci_push_part_bytes(host, buf, cnt); + + buf +=3D len; + cnt -=3D len; + + if (host->part_buf_count =3D=3D 8) { + mci_fifo_writeq_32(host->fifo_reg, host->part_buf); + host->part_buf_count =3D 0; + } + } +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS + if (unlikely((unsigned long)buf & 0x7)) { + while (cnt >=3D 8) { + u64 aligned_buf[16]; + int len =3D min(cnt & -8, (int)sizeof(aligned_buf)); + int items =3D len >> 3; + int i; + /* memcpy from input buffer into aligned buffer */ + memcpy(aligned_buf, buf, len); + buf +=3D len; + cnt -=3D len; + /* push data from aligned buffer into fifo */ + for (i =3D 0; i < items; ++i) + mci_fifo_writeq_32(host->fifo_reg, aligned_buf[i]); + } + } else +#endif + { + u64 *pdata =3D buf; + + for (; cnt >=3D 8; cnt -=3D 8) + mci_fifo_writeq_32(host->fifo_reg, *pdata++); + buf =3D pdata; + } + /* put anything remaining in the part_buf */ + if (cnt) { + dw_mci_set_part_bytes(host, buf, cnt); + /* Push data if we have reached the expected data length */ + if ((data->bytes_xfered + init_cnt) =3D=3D + (data->blksz * data->blocks)) + mci_fifo_writeq_32(host->fifo_reg, host->part_buf); + } +} + +static void dw_mci_pull_data64_32(struct dw_mci *host, void *buf, int cnt) +{ +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS + if (unlikely((unsigned long)buf & 0x7)) { + while (cnt >=3D 8) { + /* pull data from fifo into aligned buffer */ + u64 aligned_buf[16]; + int len =3D min(cnt & -8, (int)sizeof(aligned_buf)); + int items =3D len >> 3; + int i; + + for (i =3D 0; i < items; ++i) + aligned_buf[i] =3D mci_fifo_readq_32(host->fifo_reg); + + /* memcpy from aligned buffer into output buffer */ + memcpy(buf, aligned_buf, len); + buf +=3D len; + cnt -=3D len; + } + } else +#endif + { + u64 *pdata =3D buf; + + for (; cnt >=3D 8; cnt -=3D 8) + *pdata++ =3D mci_fifo_readq_32(host->fifo_reg); + buf =3D pdata; + } + if (cnt) { + host->part_buf =3D mci_fifo_readq_32(host->fifo_reg); + dw_mci_pull_final_bytes(host, buf, cnt); + } +} + static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) { int len; @@ -3239,6 +3352,9 @@ static struct dw_mci_board *dw_mci_parse_dt(struct dw= _mci *host) if (device_property_present(dev, "fifo-watermark-aligned")) host->wm_aligned =3D true; =20 + if (device_property_present(dev, "fifo-access-32bit")) + host->quirks |=3D DW_MMC_QUIRK_FIFO64_32; + if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency)) pdata->bus_hz =3D clock_frequency; =20 @@ -3367,8 +3483,13 @@ int dw_mci_probe(struct dw_mci *host) width =3D 16; host->data_shift =3D 1; } else if (i =3D=3D 2) { - host->push_data =3D dw_mci_push_data64; - host->pull_data =3D dw_mci_pull_data64; + if ((host->quirks & DW_MMC_QUIRK_FIFO64_32)) { + host->push_data =3D dw_mci_push_data64_32; + host->pull_data =3D dw_mci_pull_data64_32; + } else { + host->push_data =3D dw_mci_push_data64; + host->pull_data =3D dw_mci_pull_data64; + } width =3D 64; host->data_shift =3D 3; } else { diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h index 4ed81f94f..edd642b92 100644 --- a/drivers/mmc/host/dw_mmc.h +++ b/drivers/mmc/host/dw_mmc.h @@ -280,6 +280,8 @@ struct dw_mci_board { =20 /* Support for longer data read timeout */ #define DW_MMC_QUIRK_EXTENDED_TMOUT BIT(0) +/* Force 32-bit access to the FIFO */ +#define DW_MMC_QUIRK_FIFO64_32 BIT(1) =20 #define DW_MMC_240A 0x240a #define DW_MMC_280A 0x280a --=20 2.38.3