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[46.138.144.249]) by smtp.gmail.com with ESMTPSA id t13-20020a19ad0d000000b004d7bfd3b683sm345512lfc.17.2023.03.11.07.27.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Mar 2023 07:27:45 -0800 (PST) Message-Id: <1678548256.0817535-2-sleirsgoevy@gmail.com> In-Reply-To: <1678548256.0817535-0-sleirsgoevy@gmail.com> From: Sergey Lisov Date: Sat, 11 Mar 2023 18:22:52 +0300 Subject: [PATCH 2/2] dw_mmc: add an option to force 32-bit accesses to 64-bit device registers To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Jaehoon Chung Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" --- drivers/mmc/host/dw_mmc.c | 125 +++++++++++++++++++++++++++++++++++++- drivers/mmc/host/dw_mmc.h | 2 + 2 files changed, 125 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index 581614196..eee430620 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -2575,6 +2575,119 @@ static void dw_mci_pull_data64(struct dw_mci *host,= void *buf, int cnt) } } =20 +/* + Some dw_mmc devices have 64-bit FIFOs, but expect them to be + accessed using two 32-bit accesses. If such controller is used + with a 64-bit kernel, this has to be done explicitly. + + XXX: Is this issue specific to Exynos7? +*/ + +static inline uint64_t mci_fifo_readq_32(void __iomem *addr) +{ + uint64_t ans; + uint32_t proxy[2]; + + proxy[0] =3D mci_fifo_readl(addr); + proxy[1] =3D mci_fifo_readl(addr+4); + memcpy(&ans, proxy, 8); + return ans; +} + +static inline void mci_fifo_writeq_32(void __iomem *addr, uint64_t value) +{ + uint32_t proxy[2]; + + memcpy(proxy, &value, 8); + mci_fifo_writel(addr, proxy[0]); + mci_fifo_writel(addr+4, proxy[1]); +} + +static void dw_mci_push_data64_32(struct dw_mci *host, void *buf, int cnt) +{ + struct mmc_data *data =3D host->data; + int init_cnt =3D cnt; + + /* try and push anything in the part_buf */ + if (unlikely(host->part_buf_count)) { + int len =3D dw_mci_push_part_bytes(host, buf, cnt); + + buf +=3D len; + cnt -=3D len; + + if (host->part_buf_count =3D=3D 8) { + mci_fifo_writeq_32(host->fifo_reg, host->part_buf); + host->part_buf_count =3D 0; + } + } +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS + if (unlikely((unsigned long)buf & 0x7)) { + while (cnt >=3D 8) { + u64 aligned_buf[16]; + int len =3D min(cnt & -8, (int)sizeof(aligned_buf)); + int items =3D len >> 3; + int i; + /* memcpy from input buffer into aligned buffer */ + memcpy(aligned_buf, buf, len); + buf +=3D len; + cnt -=3D len; + /* push data from aligned buffer into fifo */ + for (i =3D 0; i < items; ++i) + mci_fifo_writeq_32(host->fifo_reg, aligned_buf[i]); + } + } else +#endif + { + u64 *pdata =3D buf; + + for (; cnt >=3D 8; cnt -=3D 8) + mci_fifo_writeq_32(host->fifo_reg, *pdata++); + buf =3D pdata; + } + /* put anything remaining in the part_buf */ + if (cnt) { + dw_mci_set_part_bytes(host, buf, cnt); + /* Push data if we have reached the expected data length */ + if ((data->bytes_xfered + init_cnt) =3D=3D + (data->blksz * data->blocks)) + mci_fifo_writeq_32(host->fifo_reg, host->part_buf); + } +} + +static void dw_mci_pull_data64_32(struct dw_mci *host, void *buf, int cnt) +{ +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS + if (unlikely((unsigned long)buf & 0x7)) { + while (cnt >=3D 8) { + /* pull data from fifo into aligned buffer */ + u64 aligned_buf[16]; + int len =3D min(cnt & -8, (int)sizeof(aligned_buf)); + int items =3D len >> 3; + int i; + + for (i =3D 0; i < items; ++i) + aligned_buf[i] =3D mci_fifo_readq_32(host->fifo_reg); + + /* memcpy from aligned buffer into output buffer */ + memcpy(buf, aligned_buf, len); + buf +=3D len; + cnt -=3D len; + } + } else +#endif + { + u64 *pdata =3D buf; + + for (; cnt >=3D 8; cnt -=3D 8) + *pdata++ =3D mci_fifo_readq_32(host->fifo_reg); + buf =3D pdata; + } + if (cnt) { + host->part_buf =3D mci_fifo_readq_32(host->fifo_reg); + dw_mci_pull_final_bytes(host, buf, cnt); + } +} + static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) { int len; @@ -3239,6 +3352,9 @@ static struct dw_mci_board *dw_mci_parse_dt(struct dw= _mci *host) if (device_property_present(dev, "fifo-watermark-aligned")) host->wm_aligned =3D true; =20 + if (device_property_present(dev, "fifo-access-32bit")) + host->quirks |=3D DW_MMC_QUIRK_FIFO64_32; + if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency)) pdata->bus_hz =3D clock_frequency; =20 @@ -3367,8 +3483,13 @@ int dw_mci_probe(struct dw_mci *host) width =3D 16; host->data_shift =3D 1; } else if (i =3D=3D 2) { - host->push_data =3D dw_mci_push_data64; - host->pull_data =3D dw_mci_pull_data64; + if ((host->quirks & DW_MMC_QUIRK_FIFO64_32)) { + host->push_data =3D dw_mci_push_data64_32; + host->pull_data =3D dw_mci_pull_data64_32; + } else { + host->push_data =3D dw_mci_push_data64; + host->pull_data =3D dw_mci_pull_data64; + } width =3D 64; host->data_shift =3D 3; } else { diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h index 4ed81f94f..edd642b92 100644 --- a/drivers/mmc/host/dw_mmc.h +++ b/drivers/mmc/host/dw_mmc.h @@ -280,6 +280,8 @@ struct dw_mci_board { =20 /* Support for longer data read timeout */ #define DW_MMC_QUIRK_EXTENDED_TMOUT BIT(0) +/* Force 32-bit access to the FIFO */ +#define DW_MMC_QUIRK_FIFO64_32 BIT(1) =20 #define DW_MMC_240A 0x240a #define DW_MMC_280A 0x280a --=20 2.38.3