From nobody Mon Apr 13 12:01:11 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9369CC6FA99 for ; Tue, 7 Mar 2023 21:13:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231343AbjCGVNP (ORCPT ); Tue, 7 Mar 2023 16:13:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231283AbjCGVNG (ORCPT ); Tue, 7 Mar 2023 16:13:06 -0500 Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 0F7E361B6; Tue, 7 Mar 2023 13:12:59 -0800 (PST) Received: from linuxonhyperv3.guj3yctzbm1etfxqx2vob5hsef.xx.internal.cloudapp.net (linux.microsoft.com [13.77.154.182]) by linux.microsoft.com (Postfix) with ESMTPSA id 4D161205761D; Tue, 7 Mar 2023 13:12:58 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 4D161205761D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1678223578; bh=dYeJBUm+62LbVH/TwEJPH+Yx+ibf1CptKPR71VNhxOQ=; h=From:To:Cc:Subject:Date:From; b=suqYlAtkuI5VehsOHjm5RLxMVpoq5bPGZ2xA+igvdcbdCU2eD2XCuchTdoAq9E3qM 5sERgL6eEjlMLE2E1xZDhycAuKC3gbuDBlASPb2/yeFwz56pbj/8YpFbdhYP5Z2O6u vUcTX/EIvs8Hy7qnG3QlAuCSUch7VKpmBHireqBc= From: Nuno Das Neves To: linux-hyperv@vger.kernel.org, linux-kernel@vger.kernel.org Cc: virtualization@lists.linux-foundation.org, mikelley@microsoft.com, kys@microsoft.com, wei.liu@kernel.org, vkuznets@redhat.com Subject: [RFC PATCH] hyperv-tlfs: Change shared HV_REGISTER_* defines to HV_SYNTHETIC_REG_* Date: Tue, 7 Mar 2023 13:12:50 -0800 Message-Id: <1678223570-25242-1-git-send-email-nunodasneves@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In x86 hyperv-tlfs, HV_REGISTER_ prefix is used to indicate MSRs accessed via rdmsrl/wrmsrl. But in ARM64, HV_REGISTER_ instead indicates VP registers accessed via get/set vp registers hypercall. This is due to HV_REGISTER_* names being used by hv_set/get_register, with the arch-specific version delegating to the appropriate mechanism. The problem is, using prefix HV_REGISTER_ for MSRs will conflict with VP registers when they are introduced for x86 in future. This patch solves the issue by: 1. Defining all the x86 MSRs with a consistent prefix: HV_X64_MSR_. This is so HV_REGISTER_ can be reserved for VP registers. 2. Change the non-arch-specific alias used by hv_set/get_register to HV_SYNTHETIC_REG. Signed-off-by: Nuno Das Neves --- arch/arm64/include/asm/hyperv-tlfs.h | 25 +++++ arch/x86/include/asm/hyperv-tlfs.h | 137 +++++++++++++-------------- arch/x86/include/asm/mshyperv.h | 8 +- arch/x86/kernel/cpu/mshyperv.c | 22 ++--- drivers/clocksource/hyperv_timer.c | 24 ++--- drivers/hv/hv.c | 32 +++---- drivers/hv/hv_common.c | 4 +- drivers/hv/vmbus_drv.c | 14 +-- include/asm-generic/mshyperv.h | 2 +- 9 files changed, 146 insertions(+), 122 deletions(-) diff --git a/arch/arm64/include/asm/hyperv-tlfs.h b/arch/arm64/include/asm/= hyperv-tlfs.h index bc6c7ac934a1..474025eb3d7e 100644 --- a/arch/arm64/include/asm/hyperv-tlfs.h +++ b/arch/arm64/include/asm/hyperv-tlfs.h @@ -64,6 +64,31 @@ #define HV_REGISTER_STIMER0_CONFIG 0x000B0000 #define HV_REGISTER_STIMER0_COUNT 0x000B0001 =20 +/* + * To support non-arch-specific code calling hv_set/get_register: + * - On x86, HV_SYNTHETIC_REG_ indicates an MSR accessed via rdmsrl/wrmsrl + * - On ARM, HV_SYNTHETIC_REG_ indicates a VP register accessed via hyperc= all + */ +#define HV_SYNTHETIC_REG_VP_INDEX (HV_REGISTER_VP_INDEX) +#define HV_SYNTHETIC_REG_TIME_REF_COUNT (HV_REGISTER_TIME_REF_COUNT) +#define HV_SYNTHETIC_REG_REFERENCE_TSC (HV_REGISTER_REFERENCE_TSC) + +#define HV_SYNTHETIC_REG_STIMER0_CONFIG (HV_REGISTER_STIMER0_CONFIG) +#define HV_SYNTHETIC_REG_STIMER0_COUNT (HV_REGISTER_STIMER0_COUNT) + +#define HV_SYNTHETIC_REG_SCONTROL (HV_REGISTER_SCONTROL) +#define HV_SYNTHETIC_REG_SIEFP (HV_REGISTER_SIEFP) +#define HV_SYNTHETIC_REG_SIMP (HV_REGISTER_SIMP) +#define HV_SYNTHETIC_REG_EOM (HV_REGISTER_EOM) +#define HV_SYNTHETIC_REG_SINT0 (HV_REGISTER_SINT0) + +#define HV_SYNTHETIC_REG_CRASH_P0 (HV_REGISTER_CRASH_P0) +#define HV_SYNTHETIC_REG_CRASH_P1 (HV_REGISTER_CRASH_P1) +#define HV_SYNTHETIC_REG_CRASH_P2 (HV_REGISTER_CRASH_P2) +#define HV_SYNTHETIC_REG_CRASH_P3 (HV_REGISTER_CRASH_P3) +#define HV_SYNTHETIC_REG_CRASH_P4 (HV_REGISTER_CRASH_P4) +#define HV_SYNTHETIC_REG_CRASH_CTL (HV_REGISTER_CRASH_CTL) + union hv_msi_entry { u64 as_uint64[2]; struct { diff --git a/arch/x86/include/asm/hyperv-tlfs.h b/arch/x86/include/asm/hype= rv-tlfs.h index 566ac26239ba..0dbb0218d0fa 100644 --- a/arch/x86/include/asm/hyperv-tlfs.h +++ b/arch/x86/include/asm/hyperv-tlfs.h @@ -178,7 +178,7 @@ enum hv_isolation_type { #define HV_X64_MSR_HYPERCALL 0x40000001 =20 /* MSR used to provide vcpu index */ -#define HV_REGISTER_VP_INDEX 0x40000002 +#define HV_X64_MSR_VP_INDEX 0x40000002 =20 /* MSR used to reset the guest OS. */ #define HV_X64_MSR_RESET 0x40000003 @@ -187,10 +187,10 @@ enum hv_isolation_type { #define HV_X64_MSR_VP_RUNTIME 0x40000010 =20 /* MSR used to read the per-partition time reference counter */ -#define HV_REGISTER_TIME_REF_COUNT 0x40000020 +#define HV_X64_MSR_TIME_REF_COUNT 0x40000020 =20 /* A partition's reference time stamp counter (TSC) page */ -#define HV_REGISTER_REFERENCE_TSC 0x40000021 +#define HV_X64_MSR_REFERENCE_TSC 0x40000021 =20 /* MSR used to retrieve the TSC frequency */ #define HV_X64_MSR_TSC_FREQUENCY 0x40000022 @@ -205,61 +205,61 @@ enum hv_isolation_type { #define HV_X64_MSR_VP_ASSIST_PAGE 0x40000073 =20 /* Define synthetic interrupt controller model specific registers. */ -#define HV_REGISTER_SCONTROL 0x40000080 -#define HV_REGISTER_SVERSION 0x40000081 -#define HV_REGISTER_SIEFP 0x40000082 -#define HV_REGISTER_SIMP 0x40000083 -#define HV_REGISTER_EOM 0x40000084 -#define HV_REGISTER_SINT0 0x40000090 -#define HV_REGISTER_SINT1 0x40000091 -#define HV_REGISTER_SINT2 0x40000092 -#define HV_REGISTER_SINT3 0x40000093 -#define HV_REGISTER_SINT4 0x40000094 -#define HV_REGISTER_SINT5 0x40000095 -#define HV_REGISTER_SINT6 0x40000096 -#define HV_REGISTER_SINT7 0x40000097 -#define HV_REGISTER_SINT8 0x40000098 -#define HV_REGISTER_SINT9 0x40000099 -#define HV_REGISTER_SINT10 0x4000009A -#define HV_REGISTER_SINT11 0x4000009B -#define HV_REGISTER_SINT12 0x4000009C -#define HV_REGISTER_SINT13 0x4000009D -#define HV_REGISTER_SINT14 0x4000009E -#define HV_REGISTER_SINT15 0x4000009F +#define HV_X64_MSR_SCONTROL 0x40000080 +#define HV_X64_MSR_SVERSION 0x40000081 +#define HV_X64_MSR_SIEFP 0x40000082 +#define HV_X64_MSR_SIMP 0x40000083 +#define HV_X64_MSR_EOM 0x40000084 +#define HV_X64_MSR_SINT0 0x40000090 +#define HV_X64_MSR_SINT1 0x40000091 +#define HV_X64_MSR_SINT2 0x40000092 +#define HV_X64_MSR_SINT3 0x40000093 +#define HV_X64_MSR_SINT4 0x40000094 +#define HV_X64_MSR_SINT5 0x40000095 +#define HV_X64_MSR_SINT6 0x40000096 +#define HV_X64_MSR_SINT7 0x40000097 +#define HV_X64_MSR_SINT8 0x40000098 +#define HV_X64_MSR_SINT9 0x40000099 +#define HV_X64_MSR_SINT10 0x4000009A +#define HV_X64_MSR_SINT11 0x4000009B +#define HV_X64_MSR_SINT12 0x4000009C +#define HV_X64_MSR_SINT13 0x4000009D +#define HV_X64_MSR_SINT14 0x4000009E +#define HV_X64_MSR_SINT15 0x4000009F =20 /* * Define synthetic interrupt controller model specific registers for * nested hypervisor. */ -#define HV_REGISTER_NESTED_SCONTROL 0x40001080 -#define HV_REGISTER_NESTED_SVERSION 0x40001081 -#define HV_REGISTER_NESTED_SIEFP 0x40001082 -#define HV_REGISTER_NESTED_SIMP 0x40001083 -#define HV_REGISTER_NESTED_EOM 0x40001084 -#define HV_REGISTER_NESTED_SINT0 0x40001090 +#define HV_X64_MSR_NESTED_SCONTROL 0x40001080 +#define HV_X64_MSR_NESTED_SVERSION 0x40001081 +#define HV_X64_MSR_NESTED_SIEFP 0x40001082 +#define HV_X64_MSR_NESTED_SIMP 0x40001083 +#define HV_X64_MSR_NESTED_EOM 0x40001084 +#define HV_X64_MSR_NESTED_SINT0 0x40001090 =20 /* * Synthetic Timer MSRs. Four timers per vcpu. */ -#define HV_REGISTER_STIMER0_CONFIG 0x400000B0 -#define HV_REGISTER_STIMER0_COUNT 0x400000B1 -#define HV_REGISTER_STIMER1_CONFIG 0x400000B2 -#define HV_REGISTER_STIMER1_COUNT 0x400000B3 -#define HV_REGISTER_STIMER2_CONFIG 0x400000B4 -#define HV_REGISTER_STIMER2_COUNT 0x400000B5 -#define HV_REGISTER_STIMER3_CONFIG 0x400000B6 -#define HV_REGISTER_STIMER3_COUNT 0x400000B7 +#define HV_X64_MSR_STIMER0_CONFIG 0x400000B0 +#define HV_X64_MSR_STIMER0_COUNT 0x400000B1 +#define HV_X64_MSR_STIMER1_CONFIG 0x400000B2 +#define HV_X64_MSR_STIMER1_COUNT 0x400000B3 +#define HV_X64_MSR_STIMER2_CONFIG 0x400000B4 +#define HV_X64_MSR_STIMER2_COUNT 0x400000B5 +#define HV_X64_MSR_STIMER3_CONFIG 0x400000B6 +#define HV_X64_MSR_STIMER3_COUNT 0x400000B7 =20 /* Hyper-V guest idle MSR */ #define HV_X64_MSR_GUEST_IDLE 0x400000F0 =20 /* Hyper-V guest crash notification MSR's */ -#define HV_REGISTER_CRASH_P0 0x40000100 -#define HV_REGISTER_CRASH_P1 0x40000101 -#define HV_REGISTER_CRASH_P2 0x40000102 -#define HV_REGISTER_CRASH_P3 0x40000103 -#define HV_REGISTER_CRASH_P4 0x40000104 -#define HV_REGISTER_CRASH_CTL 0x40000105 +#define HV_X64_MSR_CRASH_P0 0x40000100 +#define HV_X64_MSR_CRASH_P1 0x40000101 +#define HV_X64_MSR_CRASH_P2 0x40000102 +#define HV_X64_MSR_CRASH_P3 0x40000103 +#define HV_X64_MSR_CRASH_P4 0x40000104 +#define HV_X64_MSR_CRASH_CTL 0x40000105 =20 /* TSC emulation after migration */ #define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106 @@ -269,31 +269,30 @@ enum hv_isolation_type { /* TSC invariant control */ #define HV_X64_MSR_TSC_INVARIANT_CONTROL 0x40000118 =20 -/* Register name aliases for temporary compatibility */ -#define HV_X64_MSR_STIMER0_COUNT HV_REGISTER_STIMER0_COUNT -#define HV_X64_MSR_STIMER0_CONFIG HV_REGISTER_STIMER0_CONFIG -#define HV_X64_MSR_STIMER1_COUNT HV_REGISTER_STIMER1_COUNT -#define HV_X64_MSR_STIMER1_CONFIG HV_REGISTER_STIMER1_CONFIG -#define HV_X64_MSR_STIMER2_COUNT HV_REGISTER_STIMER2_COUNT -#define HV_X64_MSR_STIMER2_CONFIG HV_REGISTER_STIMER2_CONFIG -#define HV_X64_MSR_STIMER3_COUNT HV_REGISTER_STIMER3_COUNT -#define HV_X64_MSR_STIMER3_CONFIG HV_REGISTER_STIMER3_CONFIG -#define HV_X64_MSR_SCONTROL HV_REGISTER_SCONTROL -#define HV_X64_MSR_SVERSION HV_REGISTER_SVERSION -#define HV_X64_MSR_SIMP HV_REGISTER_SIMP -#define HV_X64_MSR_SIEFP HV_REGISTER_SIEFP -#define HV_X64_MSR_VP_INDEX HV_REGISTER_VP_INDEX -#define HV_X64_MSR_EOM HV_REGISTER_EOM -#define HV_X64_MSR_SINT0 HV_REGISTER_SINT0 -#define HV_X64_MSR_SINT15 HV_REGISTER_SINT15 -#define HV_X64_MSR_CRASH_P0 HV_REGISTER_CRASH_P0 -#define HV_X64_MSR_CRASH_P1 HV_REGISTER_CRASH_P1 -#define HV_X64_MSR_CRASH_P2 HV_REGISTER_CRASH_P2 -#define HV_X64_MSR_CRASH_P3 HV_REGISTER_CRASH_P3 -#define HV_X64_MSR_CRASH_P4 HV_REGISTER_CRASH_P4 -#define HV_X64_MSR_CRASH_CTL HV_REGISTER_CRASH_CTL -#define HV_X64_MSR_TIME_REF_COUNT HV_REGISTER_TIME_REF_COUNT -#define HV_X64_MSR_REFERENCE_TSC HV_REGISTER_REFERENCE_TSC +/* + * To support non-arch-specific code calling hv_set/get_register: + * - On x86, HV_SYNTHETIC_REG_ indicates an MSR accessed via rdmsrl/wrmsrl + * - On ARM, HV_SYNTHETIC_REG_ indicates a VP register accessed via hyperc= all + */ +#define HV_SYNTHETIC_REG_VP_INDEX (HV_X64_MSR_VP_INDEX) +#define HV_SYNTHETIC_REG_TIME_REF_COUNT (HV_X64_MSR_TIME_REF_COUNT) +#define HV_SYNTHETIC_REG_REFERENCE_TSC (HV_X64_MSR_REFERENCE_TSC) + +#define HV_SYNTHETIC_REG_STIMER0_CONFIG (HV_X64_MSR_STIMER0_CONFIG) +#define HV_SYNTHETIC_REG_STIMER0_COUNT (HV_X64_MSR_STIMER0_COUNT) + +#define HV_SYNTHETIC_REG_SCONTROL (HV_X64_MSR_SCONTROL) +#define HV_SYNTHETIC_REG_SIEFP (HV_X64_MSR_SIEFP) +#define HV_SYNTHETIC_REG_SIMP (HV_X64_MSR_SIMP) +#define HV_SYNTHETIC_REG_EOM (HV_X64_MSR_EOM) +#define HV_SYNTHETIC_REG_SINT0 (HV_X64_MSR_SINT0) + +#define HV_SYNTHETIC_REG_CRASH_P0 (HV_X64_MSR_CRASH_P0) +#define HV_SYNTHETIC_REG_CRASH_P1 (HV_X64_MSR_CRASH_P1) +#define HV_SYNTHETIC_REG_CRASH_P2 (HV_X64_MSR_CRASH_P2) +#define HV_SYNTHETIC_REG_CRASH_P3 (HV_X64_MSR_CRASH_P3) +#define HV_SYNTHETIC_REG_CRASH_P4 (HV_X64_MSR_CRASH_P4) +#define HV_SYNTHETIC_REG_CRASH_CTL (HV_X64_MSR_CRASH_CTL) =20 /* Hyper-V memory host visibility */ enum hv_mem_host_visibility { diff --git a/arch/x86/include/asm/mshyperv.h b/arch/x86/include/asm/mshyper= v.h index 4c4c0ec3b62e..1afa77ab9a04 100644 --- a/arch/x86/include/asm/mshyperv.h +++ b/arch/x86/include/asm/mshyperv.h @@ -224,14 +224,14 @@ extern bool hv_isolation_type_snp(void); =20 static inline bool hv_is_synic_reg(unsigned int reg) { - return (reg >=3D HV_REGISTER_SCONTROL) && - (reg <=3D HV_REGISTER_SINT15); + return (reg >=3D HV_X64_MSR_SCONTROL) && + (reg <=3D HV_X64_MSR_SINT15); } =20 static inline bool hv_is_sint_reg(unsigned int reg) { - return (reg >=3D HV_REGISTER_SINT0) && - (reg <=3D HV_REGISTER_SINT15); + return (reg >=3D HV_X64_MSR_SINT0) && + (reg <=3D HV_X64_MSR_SINT15); } =20 u64 hv_get_register(unsigned int reg); diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c index f924a76c6923..7140ee32d7be 100644 --- a/arch/x86/kernel/cpu/mshyperv.c +++ b/arch/x86/kernel/cpu/mshyperv.c @@ -45,19 +45,19 @@ struct ms_hyperv_info ms_hyperv; static inline unsigned int hv_get_nested_reg(unsigned int reg) { if (hv_is_sint_reg(reg)) - return reg - HV_REGISTER_SINT0 + HV_REGISTER_NESTED_SINT0; + return reg - HV_X64_MSR_SINT0 + HV_X64_MSR_NESTED_SINT0; =20 switch (reg) { - case HV_REGISTER_SIMP: - return HV_REGISTER_NESTED_SIMP; - case HV_REGISTER_SIEFP: - return HV_REGISTER_NESTED_SIEFP; - case HV_REGISTER_SVERSION: - return HV_REGISTER_NESTED_SVERSION; - case HV_REGISTER_SCONTROL: - return HV_REGISTER_NESTED_SCONTROL; - case HV_REGISTER_EOM: - return HV_REGISTER_NESTED_EOM; + case HV_X64_MSR_SIMP: + return HV_X64_MSR_NESTED_SIMP; + case HV_X64_MSR_SIEFP: + return HV_X64_MSR_NESTED_SIEFP; + case HV_X64_MSR_SVERSION: + return HV_X64_MSR_NESTED_SVERSION; + case HV_X64_MSR_SCONTROL: + return HV_X64_MSR_NESTED_SCONTROL; + case HV_X64_MSR_EOM: + return HV_X64_MSR_NESTED_EOM; default: return reg; } diff --git a/drivers/clocksource/hyperv_timer.c b/drivers/clocksource/hyper= v_timer.c index c0cef92b12b8..0ab3fbca34c7 100644 --- a/drivers/clocksource/hyperv_timer.c +++ b/drivers/clocksource/hyperv_timer.c @@ -81,14 +81,14 @@ static int hv_ce_set_next_event(unsigned long delta, =20 current_tick =3D hv_read_reference_counter(); current_tick +=3D delta; - hv_set_register(HV_REGISTER_STIMER0_COUNT, current_tick); + hv_set_register(HV_SYNTHETIC_REG_STIMER0_COUNT, current_tick); return 0; } =20 static int hv_ce_shutdown(struct clock_event_device *evt) { - hv_set_register(HV_REGISTER_STIMER0_COUNT, 0); - hv_set_register(HV_REGISTER_STIMER0_CONFIG, 0); + hv_set_register(HV_SYNTHETIC_REG_STIMER0_COUNT, 0); + hv_set_register(HV_SYNTHETIC_REG_STIMER0_CONFIG, 0); if (direct_mode_enabled && stimer0_irq >=3D 0) disable_percpu_irq(stimer0_irq); =20 @@ -119,7 +119,7 @@ static int hv_ce_set_oneshot(struct clock_event_device = *evt) timer_cfg.direct_mode =3D 0; timer_cfg.sintx =3D stimer0_message_sint; } - hv_set_register(HV_REGISTER_STIMER0_CONFIG, timer_cfg.as_uint64); + hv_set_register(HV_SYNTHETIC_REG_STIMER0_CONFIG, timer_cfg.as_uint64); return 0; } =20 @@ -387,7 +387,7 @@ static u64 notrace read_hv_clock_tsc(void) u64 current_tick =3D hv_read_tsc_page(hv_get_tsc_page()); =20 if (current_tick =3D=3D U64_MAX) - current_tick =3D hv_get_register(HV_REGISTER_TIME_REF_COUNT); + current_tick =3D hv_get_register(HV_SYNTHETIC_REG_TIME_REF_COUNT); =20 return current_tick; } @@ -408,9 +408,9 @@ static void suspend_hv_clock_tsc(struct clocksource *ar= g) union hv_reference_tsc_msr tsc_msr; =20 /* Disable the TSC page */ - tsc_msr.as_uint64 =3D hv_get_register(HV_REGISTER_REFERENCE_TSC); + tsc_msr.as_uint64 =3D hv_get_register(HV_SYNTHETIC_REG_REFERENCE_TSC); tsc_msr.enable =3D 0; - hv_set_register(HV_REGISTER_REFERENCE_TSC, tsc_msr.as_uint64); + hv_set_register(HV_SYNTHETIC_REG_REFERENCE_TSC, tsc_msr.as_uint64); } =20 =20 @@ -419,10 +419,10 @@ static void resume_hv_clock_tsc(struct clocksource *a= rg) union hv_reference_tsc_msr tsc_msr; =20 /* Re-enable the TSC page */ - tsc_msr.as_uint64 =3D hv_get_register(HV_REGISTER_REFERENCE_TSC); + tsc_msr.as_uint64 =3D hv_get_register(HV_SYNTHETIC_REG_REFERENCE_TSC); tsc_msr.enable =3D 1; tsc_msr.pfn =3D tsc_pfn; - hv_set_register(HV_REGISTER_REFERENCE_TSC, tsc_msr.as_uint64); + hv_set_register(HV_SYNTHETIC_REG_REFERENCE_TSC, tsc_msr.as_uint64); } =20 #ifdef HAVE_VDSO_CLOCKMODE_HVCLOCK @@ -456,7 +456,7 @@ static u64 notrace read_hv_clock_msr(void) * is set to 0 when the partition is created and is incremented in * 100 nanosecond units. */ - return hv_get_register(HV_REGISTER_TIME_REF_COUNT); + return hv_get_register(HV_SYNTHETIC_REG_TIME_REF_COUNT); } =20 static u64 notrace read_hv_clock_msr_cs(struct clocksource *arg) @@ -543,14 +543,14 @@ static bool __init hv_init_tsc_clocksource(void) * thus TSC clocksource will work even without the real TSC page * mapped. */ - tsc_msr.as_uint64 =3D hv_get_register(HV_REGISTER_REFERENCE_TSC); + tsc_msr.as_uint64 =3D hv_get_register(HV_SYNTHETIC_REG_REFERENCE_TSC); if (hv_root_partition) tsc_pfn =3D tsc_msr.pfn; else tsc_pfn =3D HVPFN_DOWN(virt_to_phys(tsc_page)); tsc_msr.enable =3D 1; tsc_msr.pfn =3D tsc_pfn; - hv_set_register(HV_REGISTER_REFERENCE_TSC, tsc_msr.as_uint64); + hv_set_register(HV_SYNTHETIC_REG_REFERENCE_TSC, tsc_msr.as_uint64); =20 clocksource_register_hz(&hyperv_cs_tsc, NSEC_PER_SEC/100); =20 diff --git a/drivers/hv/hv.c b/drivers/hv/hv.c index 8b0dd8e5244d..319f21205a9c 100644 --- a/drivers/hv/hv.c +++ b/drivers/hv/hv.c @@ -213,7 +213,7 @@ void hv_synic_enable_regs(unsigned int cpu) union hv_synic_scontrol sctrl; =20 /* Setup the Synic's message page */ - simp.as_uint64 =3D hv_get_register(HV_REGISTER_SIMP); + simp.as_uint64 =3D hv_get_register(HV_SYNTHETIC_REG_SIMP); simp.simp_enabled =3D 1; =20 if (hv_isolation_type_snp() || hv_root_partition) { @@ -227,10 +227,10 @@ void hv_synic_enable_regs(unsigned int cpu) >> HV_HYP_PAGE_SHIFT; } =20 - hv_set_register(HV_REGISTER_SIMP, simp.as_uint64); + hv_set_register(HV_SYNTHETIC_REG_SIMP, simp.as_uint64); =20 /* Setup the Synic's event page */ - siefp.as_uint64 =3D hv_get_register(HV_REGISTER_SIEFP); + siefp.as_uint64 =3D hv_get_register(HV_SYNTHETIC_REG_SIEFP); siefp.siefp_enabled =3D 1; =20 if (hv_isolation_type_snp() || hv_root_partition) { @@ -245,12 +245,12 @@ void hv_synic_enable_regs(unsigned int cpu) >> HV_HYP_PAGE_SHIFT; } =20 - hv_set_register(HV_REGISTER_SIEFP, siefp.as_uint64); + hv_set_register(HV_SYNTHETIC_REG_SIEFP, siefp.as_uint64); =20 /* Setup the shared SINT. */ if (vmbus_irq !=3D -1) enable_percpu_irq(vmbus_irq, 0); - shared_sint.as_uint64 =3D hv_get_register(HV_REGISTER_SINT0 + + shared_sint.as_uint64 =3D hv_get_register(HV_SYNTHETIC_REG_SINT0 + VMBUS_MESSAGE_SINT); =20 shared_sint.vector =3D vmbus_interrupt; @@ -266,14 +266,14 @@ void hv_synic_enable_regs(unsigned int cpu) #else shared_sint.auto_eoi =3D 0; #endif - hv_set_register(HV_REGISTER_SINT0 + VMBUS_MESSAGE_SINT, + hv_set_register(HV_SYNTHETIC_REG_SINT0 + VMBUS_MESSAGE_SINT, shared_sint.as_uint64); =20 /* Enable the global synic bit */ - sctrl.as_uint64 =3D hv_get_register(HV_REGISTER_SCONTROL); + sctrl.as_uint64 =3D hv_get_register(HV_SYNTHETIC_REG_SCONTROL); sctrl.enable =3D 1; =20 - hv_set_register(HV_REGISTER_SCONTROL, sctrl.as_uint64); + hv_set_register(HV_SYNTHETIC_REG_SCONTROL, sctrl.as_uint64); } =20 int hv_synic_init(unsigned int cpu) @@ -297,17 +297,17 @@ void hv_synic_disable_regs(unsigned int cpu) union hv_synic_siefp siefp; union hv_synic_scontrol sctrl; =20 - shared_sint.as_uint64 =3D hv_get_register(HV_REGISTER_SINT0 + + shared_sint.as_uint64 =3D hv_get_register(HV_SYNTHETIC_REG_SINT0 + VMBUS_MESSAGE_SINT); =20 shared_sint.masked =3D 1; =20 /* Need to correctly cleanup in the case of SMP!!! */ /* Disable the interrupt */ - hv_set_register(HV_REGISTER_SINT0 + VMBUS_MESSAGE_SINT, + hv_set_register(HV_SYNTHETIC_REG_SINT0 + VMBUS_MESSAGE_SINT, shared_sint.as_uint64); =20 - simp.as_uint64 =3D hv_get_register(HV_REGISTER_SIMP); + simp.as_uint64 =3D hv_get_register(HV_SYNTHETIC_REG_SIMP); /* * In Isolation VM, sim and sief pages are allocated by * paravisor. These pages also will be used by kdump @@ -322,9 +322,9 @@ void hv_synic_disable_regs(unsigned int cpu) simp.base_simp_gpa =3D 0; } =20 - hv_set_register(HV_REGISTER_SIMP, simp.as_uint64); + hv_set_register(HV_SYNTHETIC_REG_SIMP, simp.as_uint64); =20 - siefp.as_uint64 =3D hv_get_register(HV_REGISTER_SIEFP); + siefp.as_uint64 =3D hv_get_register(HV_SYNTHETIC_REG_SIEFP); siefp.siefp_enabled =3D 0; =20 if (hv_isolation_type_snp() || hv_root_partition) { @@ -334,12 +334,12 @@ void hv_synic_disable_regs(unsigned int cpu) siefp.base_siefp_gpa =3D 0; } =20 - hv_set_register(HV_REGISTER_SIEFP, siefp.as_uint64); + hv_set_register(HV_SYNTHETIC_REG_SIEFP, siefp.as_uint64); =20 /* Disable the global synic bit */ - sctrl.as_uint64 =3D hv_get_register(HV_REGISTER_SCONTROL); + sctrl.as_uint64 =3D hv_get_register(HV_SYNTHETIC_REG_SCONTROL); sctrl.enable =3D 0; - hv_set_register(HV_REGISTER_SCONTROL, sctrl.as_uint64); + hv_set_register(HV_SYNTHETIC_REG_SCONTROL, sctrl.as_uint64); =20 if (vmbus_irq !=3D -1) disable_percpu_irq(vmbus_irq); diff --git a/drivers/hv/hv_common.c b/drivers/hv/hv_common.c index 52a6f89ccdbd..77a68f16bc6e 100644 --- a/drivers/hv/hv_common.c +++ b/drivers/hv/hv_common.c @@ -142,7 +142,7 @@ int hv_common_cpu_init(unsigned int cpu) *outputarg =3D (char *)(*inputarg) + HV_HYP_PAGE_SIZE; } =20 - msr_vp_index =3D hv_get_register(HV_REGISTER_VP_INDEX); + msr_vp_index =3D hv_get_register(HV_SYNTHETIC_REG_VP_INDEX); =20 hv_vp_index[cpu] =3D msr_vp_index; =20 @@ -246,7 +246,7 @@ EXPORT_SYMBOL_GPL(hv_is_hibernation_supported); */ static u64 __hv_read_ref_counter(void) { - return hv_get_register(HV_REGISTER_TIME_REF_COUNT); + return hv_get_register(HV_SYNTHETIC_REG_TIME_REF_COUNT); } =20 u64 (*hv_read_reference_counter)(void) =3D __hv_read_ref_counter; diff --git a/drivers/hv/vmbus_drv.c b/drivers/hv/vmbus_drv.c index 1901556efe79..9ca8a7b73b81 100644 --- a/drivers/hv/vmbus_drv.c +++ b/drivers/hv/vmbus_drv.c @@ -1405,17 +1405,17 @@ static void hv_kmsg_dump(struct kmsg_dumper *dumper, * contain the size of the panic data in that page. Rest of the * registers are no-op when the NOTIFY_MSG flag is set. */ - hv_set_register(HV_REGISTER_CRASH_P0, 0); - hv_set_register(HV_REGISTER_CRASH_P1, 0); - hv_set_register(HV_REGISTER_CRASH_P2, 0); - hv_set_register(HV_REGISTER_CRASH_P3, virt_to_phys(hv_panic_page)); - hv_set_register(HV_REGISTER_CRASH_P4, bytes_written); + hv_set_register(HV_SYNTHETIC_REG_CRASH_P0, 0); + hv_set_register(HV_SYNTHETIC_REG_CRASH_P1, 0); + hv_set_register(HV_SYNTHETIC_REG_CRASH_P2, 0); + hv_set_register(HV_SYNTHETIC_REG_CRASH_P3, virt_to_phys(hv_panic_page)); + hv_set_register(HV_SYNTHETIC_REG_CRASH_P4, bytes_written); =20 /* * Let Hyper-V know there is crash data available along with * the panic message. */ - hv_set_register(HV_REGISTER_CRASH_CTL, + hv_set_register(HV_SYNTHETIC_REG_CRASH_CTL, (HV_CRASH_CTL_CRASH_NOTIFY | HV_CRASH_CTL_CRASH_NOTIFY_MSG)); } =20 @@ -1555,7 +1555,7 @@ static int vmbus_bus_init(void) * Register for panic kmsg callback only if the right * capability is supported by the hypervisor. */ - hyperv_crash_ctl =3D hv_get_register(HV_REGISTER_CRASH_CTL); + hyperv_crash_ctl =3D hv_get_register(HV_SYNTHETIC_REG_CRASH_CTL); if (hyperv_crash_ctl & HV_CRASH_CTL_CRASH_NOTIFY_MSG) hv_kmsg_dump_register(); =20 diff --git a/include/asm-generic/mshyperv.h b/include/asm-generic/mshyperv.h index 8845a2eca339..76bf968d77a8 100644 --- a/include/asm-generic/mshyperv.h +++ b/include/asm-generic/mshyperv.h @@ -147,7 +147,7 @@ static inline void vmbus_signal_eom(struct hv_message *= msg, u32 old_msg_type) * possibly deliver another msg from the * hypervisor */ - hv_set_register(HV_REGISTER_EOM, 0); + hv_set_register(HV_SYNTHETIC_REG_EOM, 0); } } =20 --=20 2.25.1