From nobody Fri Sep 12 04:38:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B3C1C636D4 for ; Mon, 13 Feb 2023 18:27:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231363AbjBMS1F (ORCPT ); Mon, 13 Feb 2023 13:27:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46614 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230199AbjBMS03 (ORCPT ); Mon, 13 Feb 2023 13:26:29 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E600A134; Mon, 13 Feb 2023 10:26:27 -0800 (PST) Date: Mon, 13 Feb 2023 18:26:24 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1676312784; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=R19Sizvsj0tF7RIZZbwYMnxHMhZAMPMsli2XLiDUCXM=; b=0u33PN8FuceNGPgBKCzr9YuOuYlrrAZYAYDBlW7Z6VZwZb01YhR9grJnQOWf2YLch3Anoz mUq0K9l8X2pgig2kMBygT5dYYKFjKLfvFiVh/X/3WYGSURUyHp9bNN+8ZLNujm7K/U1FbC aWlPr1NgbJFDXIPMbZoI/9aI0gbVa2UnEFqFztwEM0bS3HH+HcYhQEKZvpUD3L3AicOtVh /TfSBPrZoQXlGL9v33AMJGgMcCfJd/1l1pFBvb55+Jybn23O0rc68bCrCiPkvG03bmTvJ2 CEWLh7WPL80PKvJ/XGSRJMDPSoq8NvDk94TXDEO0/Hzlt3GtQs5lum/ViBxmfg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1676312784; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=R19Sizvsj0tF7RIZZbwYMnxHMhZAMPMsli2XLiDUCXM=; b=HdBmxqz+Kcl9EYDktexRDmZcwgNaH5IP1rq4ReY9Jby6yqyFVm6uzTMpMxRqacUJD4ufjv ZdUvbWHisZsn0NDA== From: "tip-bot2 for Samuel Holland" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: timers/core] clocksource/drivers/riscv: Increase the clock source rating Cc: Samuel Holland , Palmer Dabbelt , Anup Patel , Lad Prabhakar , Daniel Lezcano , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20221228004444.61568-1-samuel@sholland.org> References: <20221228004444.61568-1-samuel@sholland.org> MIME-Version: 1.0 Message-ID: <167631278448.4906.3061443798172284718.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the timers/core branch of tip: Commit-ID: 674402b0098b66b8ba91fe93c0d27af703256098 Gitweb: https://git.kernel.org/tip/674402b0098b66b8ba91fe93c0d27af70= 3256098 Author: Samuel Holland AuthorDate: Tue, 27 Dec 2022 18:44:44 -06:00 Committer: Daniel Lezcano CommitterDate: Mon, 13 Feb 2023 13:10:16 +01:00 clocksource/drivers/riscv: Increase the clock source rating RISC-V provides an architectural clock source via the time CSR. This clock source exposes a 64-bit counter synchronized across all CPUs. Because it is accessed using a CSR, it is much more efficient to read than MMIO clock sources. For example, on the Allwinner D1, reading the sun4i timer in a loop takes 131 cycles/iteration, while reading the RISC-V time CSR takes only 5 cycles/iteration. Adjust the RISC-V clock source rating so it is preferred over the various platform-specific MMIO clock sources. Signed-off-by: Samuel Holland Acked-by: Palmer Dabbelt Reviewed-by: Palmer Dabbelt Reviewed-by: Anup Patel Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20221228004444.61568-1-samuel@sholland.org Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-riscv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-= riscv.c index 1b4b36d..adf7f98 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -74,7 +74,7 @@ static u64 notrace riscv_sched_clock(void) =20 static struct clocksource riscv_clocksource =3D { .name =3D "riscv_clocksource", - .rating =3D 300, + .rating =3D 400, .mask =3D CLOCKSOURCE_MASK(64), .flags =3D CLOCK_SOURCE_IS_CONTINUOUS, .read =3D riscv_clocksource_rdtime,