From nobody Sat Sep 13 01:47:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C53FC61DA4 for ; Mon, 6 Feb 2023 13:00:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230223AbjBFNAR (ORCPT ); Mon, 6 Feb 2023 08:00:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42390 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230196AbjBFNAL (ORCPT ); Mon, 6 Feb 2023 08:00:11 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 18A7723326; Mon, 6 Feb 2023 05:00:09 -0800 (PST) Date: Mon, 06 Feb 2023 13:00:05 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1675688406; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=PEIq5IFNtGsUPsG0wsMPoSRidRh0YOa3DY1/lxlVxtk=; b=3o010HnIpgHSPzMS+T9SqDuETKyC8Xa5+Odv/qXcs3Cg4l0peCAPe5jArOw8IBkQN94KQh +sXfjxuu16OB1fw7z+h3Vy+Hu4mXfZ3hz39x1AjYIH1zNmwC/oMjSevVdps6gWDqfGcd9X 8GKaS+qcg++fnoclEgoPUPu2Yw5JGivaRwh25M/fkqBtLzwyXVCLyiaTqEArMdGsxvx4F2 eF/S13ZkFheiVlFd6hGbwyfTMwHaAzF2b7oihoZGvA/KN4f3HjmTemjv9GaKZD5CktBQBe KSNiJDqPpe3G/rIfsmJOnLgA0M2Y3Sv27/TEDx/vvnyF42MQivmrW6gduCmhJw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1675688406; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=PEIq5IFNtGsUPsG0wsMPoSRidRh0YOa3DY1/lxlVxtk=; b=eeyZPsvXxd4UQajsgwGUkYbPOlINOefaLNmf7BYmVn5K+V2Jb9XB7xJx5E8T/knNlnYnqx JX54dhg8sFYOMbDA== From: "tip-bot2 for Borislav Petkov (AMD)" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/microcode] x86/microcode/AMD: Fix mixed steppings support Cc: "Borislav Petkov (AMD)" , , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20230130161709.11615-4-bp@alien8.de> References: <20230130161709.11615-4-bp@alien8.de> MIME-Version: 1.0 Message-ID: <167568840579.4906.7552480093445585238.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the x86/microcode branch of tip: Commit-ID: 7ff6edf4fef38ab404ee7861f257e28eaaeed35f Gitweb: https://git.kernel.org/tip/7ff6edf4fef38ab404ee7861f257e28ea= aeed35f Author: Borislav Petkov (AMD) AuthorDate: Thu, 26 Jan 2023 16:26:17 +01:00 Committer: Borislav Petkov (AMD) CommitterDate: Mon, 06 Feb 2023 13:40:16 +01:00 x86/microcode/AMD: Fix mixed steppings support The AMD side of the loader has always claimed to support mixed steppings. But somewhere along the way, it broke that by assuming that the cached patch blob is a single one instead of it being one per *node*. So turn it into a per-node one so that each node can stash the blob relevant for it. [ NB: Fixes tag is not really the exactly correct one but it is good enough. ] Fixes: fe055896c040 ("x86/microcode: Merge the early microcode loader") Signed-off-by: Borislav Petkov (AMD) Cc: # 2355370cd941 ("x86/microcode/amd: Remove load_mic= rocode_amd()'s bsp parameter") Cc: # a5ad92134bd1 ("x86/microcode/AMD: Add a @cpu para= meter to the reloading functions") Link: https://lore.kernel.org/r/20230130161709.11615-4-bp@alien8.de --- arch/x86/kernel/cpu/microcode/amd.c | 34 +++++++++++++++++----------- 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/micr= ocode/amd.c index 1023be6..9eb457b 100644 --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -55,7 +55,9 @@ struct cont_desc { }; =20 static u32 ucode_new_rev; -static u8 amd_ucode_patch[PATCH_MAX_SIZE]; + +/* One blob per node. */ +static u8 amd_ucode_patch[MAX_NUMNODES][PATCH_MAX_SIZE]; =20 /* * Microcode patch container file is prepended to the initrd in cpio @@ -428,7 +430,7 @@ static bool early_apply_microcode(u32 cpuid_1_eax, void= *ucode, size_t size, boo patch =3D (u8 (*)[PATCH_MAX_SIZE])__pa_nodebug(&amd_ucode_patch); #else new_rev =3D &ucode_new_rev; - patch =3D &amd_ucode_patch; + patch =3D &amd_ucode_patch[0]; #endif =20 desc.cpuid_1_eax =3D cpuid_1_eax; @@ -580,10 +582,10 @@ int __init save_microcode_in_initrd_amd(unsigned int = cpuid_1_eax) =20 void reload_ucode_amd(unsigned int cpu) { - struct microcode_amd *mc; u32 rev, dummy __always_unused; + struct microcode_amd *mc; =20 - mc =3D (struct microcode_amd *)amd_ucode_patch; + mc =3D (struct microcode_amd *)amd_ucode_patch[cpu_to_node(cpu)]; =20 rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); =20 @@ -852,6 +854,8 @@ static enum ucode_state __load_microcode_amd(u8 family,= const u8 *data, =20 static enum ucode_state load_microcode_amd(u8 family, const u8 *data, size= _t size) { + struct cpuinfo_x86 *c; + unsigned int nid, cpu; struct ucode_patch *p; enum ucode_state ret; =20 @@ -864,18 +868,22 @@ static enum ucode_state load_microcode_amd(u8 family,= const u8 *data, size_t siz return ret; } =20 - p =3D find_patch(0); - if (!p) { - return ret; - } else { - if (boot_cpu_data.microcode >=3D p->patch_id) - return ret; + for_each_node(nid) { + cpu =3D cpumask_first(cpumask_of_node(nid)); + c =3D &cpu_data(cpu); + + p =3D find_patch(cpu); + if (!p) + continue; + + if (c->microcode >=3D p->patch_id) + continue; =20 ret =3D UCODE_NEW; - } =20 - memset(amd_ucode_patch, 0, PATCH_MAX_SIZE); - memcpy(amd_ucode_patch, p->data, min_t(u32, p->size, PATCH_MAX_SIZE)); + memset(&amd_ucode_patch[nid], 0, PATCH_MAX_SIZE); + memcpy(&amd_ucode_patch[nid], p->data, min_t(u32, p->size, PATCH_MAX_SIZ= E)); + } =20 return ret; }