From nobody Sat Sep 13 18:29:31 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C19C6C38142 for ; Tue, 31 Jan 2023 14:23:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231851AbjAaOXd (ORCPT ); Tue, 31 Jan 2023 09:23:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54442 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231211AbjAaOXI (ORCPT ); Tue, 31 Jan 2023 09:23:08 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 204EF51428; Tue, 31 Jan 2023 06:22:43 -0800 (PST) Date: Tue, 31 Jan 2023 14:22:41 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1675174961; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BOHBAW2gkpF4r6MXGfT0rKDufGJiVnmYnix2uPGRy5g=; b=wonekLYXwEHCQYvlF/YrqwqikWkYA/EfSoOFEk+6UsD+a8CRYDE1NWXqNmBMt8IASZPn4F mGtYCQUCb91Q9nHfe55nfyTWdpafhVuJOIG1nRXa3tF1yHQkYXb4+fDp4LIblw8Pu6JEpW YfwFwUuxmnKlstpZcZpNRdOe57xVC0euuELWZhyEXfVgLfXysNgoitEoLVaExwWk6Ywbki sYEHPjc56hV0jj4UhApGgETj63hgCA06daRy1A8EcRe+l9P668DVJNVIQ4nkjCT6RQdtCa N80oMPfKWjZdgLMsDzLEHb2PmBkvMEznDagR6g7amitwwMmOv+XgIZD/48Iu/A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1675174961; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BOHBAW2gkpF4r6MXGfT0rKDufGJiVnmYnix2uPGRy5g=; b=Cq18WoMxZ128BHtdFk4wK4AizIVfNai1jIhQF1ZxVLmFJ5NzVA3TsQXgwoIlKbpFBGEBzP FCdxX8oqXmiDppCg== From: "tip-bot2 for Peter Zijlstra" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/alternatives] x86/alternatives: Teach text_poke_bp() to patch Jcc.d32 instructions Cc: "Peter Zijlstra (Intel)" , Ingo Molnar , "Masami Hiramatsu (Google)" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20230123210607.115718513@infradead.org> References: <20230123210607.115718513@infradead.org> MIME-Version: 1.0 Message-ID: <167517496132.4906.7165599563427710228.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the x86/alternatives branch of ti= p: Commit-ID: ac0ee0a9560c97fa5fe1409e450c2425d4ebd17a Gitweb: https://git.kernel.org/tip/ac0ee0a9560c97fa5fe1409e450c2425d= 4ebd17a Author: Peter Zijlstra AuthorDate: Mon, 23 Jan 2023 21:59:17 +01:00 Committer: Ingo Molnar CommitterDate: Tue, 31 Jan 2023 15:05:31 +01:00 x86/alternatives: Teach text_poke_bp() to patch Jcc.d32 instructions In order to re-write Jcc.d32 instructions text_poke_bp() needs to be taught about them. The biggest hurdle is that the whole machinery is currently made for 5 byte instructions and extending this would grow struct text_poke_loc which is currently a nice 16 bytes and used in an array. However, since text_poke_loc contains a full copy of the (s32) displacement, it is possible to map the Jcc.d32 2 byte opcodes to Jcc.d8 1 byte opcode for the int3 emulation. This then leaves the replacement bytes; fudge that by only storing the last 5 bytes and adding the rule that 'length =3D=3D 6' instruction will be prefixed with a 0x0f byte. Signed-off-by: Peter Zijlstra (Intel) Signed-off-by: Ingo Molnar Reviewed-by: Masami Hiramatsu (Google) Link: https://lore.kernel.org/r/20230123210607.115718513@infradead.org --- arch/x86/kernel/alternative.c | 62 +++++++++++++++++++++++++--------- 1 file changed, 47 insertions(+), 15 deletions(-) diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c index 9a45aa1..f615e0c 100644 --- a/arch/x86/kernel/alternative.c +++ b/arch/x86/kernel/alternative.c @@ -338,6 +338,12 @@ next: } } =20 +static inline bool is_jcc32(struct insn *insn) +{ + /* Jcc.d32 second opcode byte is in the range: 0x80-0x8f */ + return insn->opcode.bytes[0] =3D=3D 0x0f && (insn->opcode.bytes[1] & 0xf0= ) =3D=3D 0x80; +} + #if defined(CONFIG_RETPOLINE) && defined(CONFIG_OBJTOOL) =20 /* @@ -376,12 +382,6 @@ static int emit_indirect(int op, int reg, u8 *bytes) return i; } =20 -static inline bool is_jcc32(struct insn *insn) -{ - /* Jcc.d32 second opcode byte is in the range: 0x80-0x8f */ - return insn->opcode.bytes[0] =3D=3D 0x0f && (insn->opcode.bytes[1] & 0xf0= ) =3D=3D 0x80; -} - static int emit_call_track_retpoline(void *addr, struct insn *insn, int re= g, u8 *bytes) { u8 op =3D insn->opcode.bytes[0]; @@ -1770,6 +1770,11 @@ void text_poke_sync(void) on_each_cpu(do_sync_core, NULL, 1); } =20 +/* + * NOTE: crazy scheme to allow patching Jcc.d32 but not increase the size = of + * this thing. When len =3D=3D 6 everything is prefixed with 0x0f and we m= ap + * opcode to Jcc.d8, using len to distinguish. + */ struct text_poke_loc { /* addr :=3D _stext + rel_addr */ s32 rel_addr; @@ -1891,6 +1896,10 @@ noinstr int poke_int3_handler(struct pt_regs *regs) int3_emulate_jmp(regs, (long)ip + tp->disp); break; =20 + case 0x70 ... 0x7f: /* Jcc */ + int3_emulate_jcc(regs, tp->opcode & 0xf, (long)ip, tp->disp); + break; + default: BUG(); } @@ -1964,16 +1973,26 @@ static void text_poke_bp_batch(struct text_poke_loc= *tp, unsigned int nr_entries * Second step: update all but the first byte of the patched range. */ for (do_sync =3D 0, i =3D 0; i < nr_entries; i++) { - u8 old[POKE_MAX_OPCODE_SIZE] =3D { tp[i].old, }; + u8 old[POKE_MAX_OPCODE_SIZE+1] =3D { tp[i].old, }; + u8 _new[POKE_MAX_OPCODE_SIZE+1]; + const u8 *new =3D tp[i].text; int len =3D tp[i].len; =20 if (len - INT3_INSN_SIZE > 0) { memcpy(old + INT3_INSN_SIZE, text_poke_addr(&tp[i]) + INT3_INSN_SIZE, len - INT3_INSN_SIZE); + + if (len =3D=3D 6) { + _new[0] =3D 0x0f; + memcpy(_new + 1, new, 5); + new =3D _new; + } + text_poke(text_poke_addr(&tp[i]) + INT3_INSN_SIZE, - (const char *)tp[i].text + INT3_INSN_SIZE, + new + INT3_INSN_SIZE, len - INT3_INSN_SIZE); + do_sync++; } =20 @@ -2001,8 +2020,7 @@ static void text_poke_bp_batch(struct text_poke_loc *= tp, unsigned int nr_entries * The old instruction is recorded so that the event can be * processed forwards or backwards. */ - perf_event_text_poke(text_poke_addr(&tp[i]), old, len, - tp[i].text, len); + perf_event_text_poke(text_poke_addr(&tp[i]), old, len, new, len); } =20 if (do_sync) { @@ -2019,10 +2037,15 @@ static void text_poke_bp_batch(struct text_poke_loc= *tp, unsigned int nr_entries * replacing opcode. */ for (do_sync =3D 0, i =3D 0; i < nr_entries; i++) { - if (tp[i].text[0] =3D=3D INT3_INSN_OPCODE) + u8 byte =3D tp[i].text[0]; + + if (tp[i].len =3D=3D 6) + byte =3D 0x0f; + + if (byte =3D=3D INT3_INSN_OPCODE) continue; =20 - text_poke(text_poke_addr(&tp[i]), tp[i].text, INT3_INSN_SIZE); + text_poke(text_poke_addr(&tp[i]), &byte, INT3_INSN_SIZE); do_sync++; } =20 @@ -2040,9 +2063,11 @@ static void text_poke_loc_init(struct text_poke_loc = *tp, void *addr, const void *opcode, size_t len, const void *emulate) { struct insn insn; - int ret, i; + int ret, i =3D 0; =20 - memcpy((void *)tp->text, opcode, len); + if (len =3D=3D 6) + i =3D 1; + memcpy((void *)tp->text, opcode+i, len-i); if (!emulate) emulate =3D opcode; =20 @@ -2053,6 +2078,13 @@ static void text_poke_loc_init(struct text_poke_loc = *tp, void *addr, tp->len =3D len; tp->opcode =3D insn.opcode.bytes[0]; =20 + if (is_jcc32(&insn)) { + /* + * Map Jcc.d32 onto Jcc.d8 and use len to distinguish. + */ + tp->opcode =3D insn.opcode.bytes[1] - 0x10; + } + switch (tp->opcode) { case RET_INSN_OPCODE: case JMP32_INSN_OPCODE: @@ -2069,7 +2101,6 @@ static void text_poke_loc_init(struct text_poke_loc *= tp, void *addr, BUG_ON(len !=3D insn.length); } =20 - switch (tp->opcode) { case INT3_INSN_OPCODE: case RET_INSN_OPCODE: @@ -2078,6 +2109,7 @@ static void text_poke_loc_init(struct text_poke_loc *= tp, void *addr, case CALL_INSN_OPCODE: case JMP32_INSN_OPCODE: case JMP8_INSN_OPCODE: + case 0x70 ... 0x7f: /* Jcc */ tp->disp =3D insn.immediate.value; break;