From nobody Sat Sep 21 05:31:08 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5D1AC636D3 for ; Tue, 31 Jan 2023 02:00:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231297AbjAaB7x (ORCPT ); Mon, 30 Jan 2023 20:59:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36268 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231182AbjAaB7o (ORCPT ); Mon, 30 Jan 2023 20:59:44 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9B13832E60 for ; Mon, 30 Jan 2023 17:59:31 -0800 (PST) X-UUID: e36df0f0a10a11eda06fc9ecc4dadd91-20230131 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=O16xl6hxIEmlemO1iJ5si/8tOcwHZCvsl61zX8Je9UM=; b=BEROY7+0E7jGtHv5JpTjlFZitUzZUgw/IKqIHSJkDmRpCipHWXc1SCQGKbRlJJOJKs/+nHW+vQXXO9Y4tf166isAkLt5IQe+Q99FIB8BCKOS7OYfHcCNonyQ1v8OW8KXXHcm6+xnib5r5g9Tqp/Mspd/LGgbs4/qGMs5qIrWavg=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.18,REQID:feab385b-e293-48e9-b8da-9cc77bb690ea,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:90 X-CID-INFO: VERSION:1.1.18,REQID:feab385b-e293-48e9-b8da-9cc77bb690ea,IP:0,URL :0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:90 X-CID-META: VersionHash:3ca2d6b,CLOUDID:506cf6f6-ff42-4fb0-b929-626456a83c14,B ulkID:2301310959280E7QZAWM,BulkQuantity:0,Recheck:0,SF:38|29|28|17|19|48,T C:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 ,OSI:0,OSA:0 X-CID-BVR: 0,NGT X-UUID: e36df0f0a10a11eda06fc9ecc4dadd91-20230131 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 310778411; Tue, 31 Jan 2023 09:59:25 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Tue, 31 Jan 2023 09:59:24 +0800 Received: from mszsdaap41.gcn.mediatek.inc (10.16.6.141) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Tue, 31 Jan 2023 09:59:23 +0800 From: To: , , , , , , , , CC: , , , , , Xinlei Lee Subject: [PATCH v3 1/2] drm/panel: boe-tv101wum-nl6: Remove extra delay Date: Tue, 31 Jan 2023 09:59:18 +0800 Message-ID: <1675130359-24459-2-git-send-email-xinlei.lee@mediatek.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1675130359-24459-1-git-send-email-xinlei.lee@mediatek.com> References: <1675130359-24459-1-git-send-email-xinlei.lee@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xinlei Lee Reduce the delay after LCM reset by removing an extra delay in the initialization commands array. The required delay of at least 6ms after reset is guaranteed by boe_panel_prepare(). Signed-off-by: Xinlei Lee Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c b/drivers/gpu/d= rm/panel/panel-boe-tv101wum-nl6.c index 857a2f0420d7..f0093035f1ff 100644 --- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c +++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c @@ -780,7 +780,6 @@ static const struct panel_init_cmd inx_hj110iz_init_cmd= [] =3D { }; =20 static const struct panel_init_cmd boe_init_cmd[] =3D { - _INIT_DELAY_CMD(24), _INIT_DCS_CMD(0xB0, 0x05), _INIT_DCS_CMD(0xB1, 0xE5), _INIT_DCS_CMD(0xB3, 0x52), --=20 2.18.0 From nobody Sat Sep 21 05:31:08 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8DB57C636D3 for ; Tue, 31 Jan 2023 02:00:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231222AbjAaCAS (ORCPT ); Mon, 30 Jan 2023 21:00:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36258 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231164AbjAaB7n (ORCPT ); Mon, 30 Jan 2023 20:59:43 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 319682686B for ; Mon, 30 Jan 2023 17:59:30 -0800 (PST) X-UUID: e493b4d8a10a11ed945fc101203acc17-20230131 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=BoWoQMdNfjipELBRS3LNoduY6UIoypqp210tmpmIGPc=; b=RH9r+iTh0e3vkkQw9TUn+sauGOAeqXhE6xAkv7t9YgzfL+wW5a6OSBoJJ1moDGNdf8t4PtpDWvsD/nGpnSRK8LqFgKgTZWoocTtd/q4QEMl8LYiszr6C15fimPHJKTo2whodsE7xa/OyBLKy0aqYvpaVmBXM7NsN2w7tmw2adrI=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.18,REQID:85b23dd6-524d-4ef6-b124-cee6ed76b900,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:90 X-CID-INFO: VERSION:1.1.18,REQID:85b23dd6-524d-4ef6-b124-cee6ed76b900,IP:0,URL :0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:90 X-CID-META: VersionHash:3ca2d6b,CLOUDID:c56b678d-8530-4eff-9f77-222cf6e2895b,B ulkID:23013109592761N1B6JK,BulkQuantity:0,Recheck:0,SF:38|29|28|17|19|48,T C:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 ,OSI:0,OSA:0 X-CID-BVR: 0 X-UUID: e493b4d8a10a11ed945fc101203acc17-20230131 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1148795063; Tue, 31 Jan 2023 09:59:27 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Tue, 31 Jan 2023 09:59:26 +0800 Received: from mszsdaap41.gcn.mediatek.inc (10.16.6.141) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Tue, 31 Jan 2023 09:59:25 +0800 From: To: , , , , , , , , CC: , , , , , Xinlei Lee Subject: [PATCH v3 2/2] drm/panel: boe-tv101wum-nl6: Fine tune the panel power sequence Date: Tue, 31 Jan 2023 09:59:19 +0800 Message-ID: <1675130359-24459-3-git-send-email-xinlei.lee@mediatek.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1675130359-24459-1-git-send-email-xinlei.lee@mediatek.com> References: <1675130359-24459-1-git-send-email-xinlei.lee@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xinlei Lee For "boe,tv105wum-nw0" this special panel, it is stipulated in the panel spec that MIPI needs to keep the LP11 state before the lcm_reset pin is pulled high. Signed-off-by: Xinlei Lee Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c b/drivers/gpu/d= rm/panel/panel-boe-tv101wum-nl6.c index f0093035f1ff..67df61de64ae 100644 --- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c +++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c @@ -36,6 +36,7 @@ struct panel_desc { const struct panel_init_cmd *init_cmds; unsigned int lanes; bool discharge_on_disable; + bool lp11_before_reset; }; =20 struct boe_panel { @@ -1261,6 +1262,10 @@ static int boe_panel_prepare(struct drm_panel *panel) =20 usleep_range(10000, 11000); =20 + if (boe->desc->lp11_before_reset) { + mipi_dsi_dcs_nop(boe->dsi); + usleep_range(1000, 2000); + } gpiod_set_value(boe->enable_gpio, 1); usleep_range(1000, 2000); gpiod_set_value(boe->enable_gpio, 0); @@ -1487,6 +1492,7 @@ static const struct panel_desc boe_tv105wum_nw0_desc = =3D { .mode_flags =3D MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_LPM, .init_cmds =3D boe_init_cmd, + .lp11_before_reset =3D true, }; =20 static int boe_panel_get_modes(struct drm_panel *panel, --=20 2.18.0