From nobody Sat Sep 13 22:27:32 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DDE3AC54EAA for ; Mon, 30 Jan 2023 03:57:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235362AbjA3D5n (ORCPT ); Sun, 29 Jan 2023 22:57:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47168 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235290AbjA3D5e (ORCPT ); Sun, 29 Jan 2023 22:57:34 -0500 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8DF3199DD; Sun, 29 Jan 2023 19:57:33 -0800 (PST) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 84050201A4A; Mon, 30 Jan 2023 04:57:32 +0100 (CET) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 4DBD320087C; Mon, 30 Jan 2023 04:57:32 +0100 (CET) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 8065C183ABEF; Mon, 30 Jan 2023 11:57:30 +0800 (+08) From: Richard Zhu To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, l.stach@pengutronix.de, shawnguo@kernel.org, lorenzo.pieralisi@arm.com, peng.fan@nxp.com, marex@denx.de, marcel.ziswiler@toradex.com, tharvey@gateworks.com, frank.li@nxp.com Cc: hongxing.zhu@nxp.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com Subject: [PATCH v7 1/5] dt-bindings: imx6q-pcie: Prepare to separate the Endpoint binding document Date: Mon, 30 Jan 2023 11:32:15 +0800 Message-Id: <1675049539-14976-2-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1675049539-14976-1-git-send-email-hongxing.zhu@nxp.com> References: <1675049539-14976-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Prepare to create one separate DT-schema for i.MX PCIe Endpoint controllers in another commit. Remove the EP mode compatible, and update the description. Signed-off-by: Richard Zhu --- .../devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Do= cumentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index f13f87fddb3d..2985d14b9ecc 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -13,6 +13,11 @@ maintainers: description: |+ This PCIe host controller is based on the Synopsys DesignWare PCIe IP and thus inherits all the common properties defined in snps,dw-pcie.yaml. + The controller instances are dual mode where in they can work either in + Root Port mode or Endpoint mode but one at a time. + + See fsl,imx6q-pcie-ep.yaml for details on the Endpoint mode device tree + bindings. =20 properties: compatible: @@ -24,9 +29,6 @@ properties: - fsl,imx8mq-pcie - fsl,imx8mm-pcie - fsl,imx8mp-pcie - - fsl,imx8mm-pcie-ep - - fsl,imx8mq-pcie-ep - - fsl,imx8mp-pcie-ep =20 reg: items: @@ -178,6 +180,7 @@ required: =20 allOf: - $ref: /schemas/pci/snps,dw-pcie.yaml# + - if: properties: compatible: --=20 2.34.1 From nobody Sat Sep 13 22:27:32 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DEF17C54EAA for ; Mon, 30 Jan 2023 03:57:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231137AbjA3D5s (ORCPT ); Sun, 29 Jan 2023 22:57:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47328 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235393AbjA3D5h (ORCPT ); Sun, 29 Jan 2023 22:57:37 -0500 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F187199CF; Sun, 29 Jan 2023 19:57:35 -0800 (PST) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 0FD52201E24; Mon, 30 Jan 2023 04:57:34 +0100 (CET) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id A62A920087C; Mon, 30 Jan 2023 04:57:33 +0100 (CET) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id D8B28180222F; Mon, 30 Jan 2023 11:57:31 +0800 (+08) From: Richard Zhu To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, l.stach@pengutronix.de, shawnguo@kernel.org, lorenzo.pieralisi@arm.com, peng.fan@nxp.com, marex@denx.de, marcel.ziswiler@toradex.com, tharvey@gateworks.com, frank.li@nxp.com Cc: hongxing.zhu@nxp.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com Subject: [PATCH v7 2/5] dt-bindings: imx6q-pcie: Add schema for i.MX8M PCIe Endpoint modes Date: Mon, 30 Jan 2023 11:32:16 +0800 Message-Id: <1675049539-14976-3-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1675049539-14976-1-git-send-email-hongxing.zhu@nxp.com> References: <1675049539-14976-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for i.MX8M PCIe Endpoint modes, and update the MAINTAINER accordingly. Signed-off-by: Richard Zhu --- .../bindings/pci/fsl,imx6q-pcie-ep.yaml | 317 ++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 318 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep= .yaml diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml b= /Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml new file mode 100644 index 000000000000..7c594ae53067 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml @@ -0,0 +1,317 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX6 PCIe Endpoint controller + +maintainers: + - Lucas Stach + - Richard Zhu + +description: |+ + This PCIe controller is based on the Synopsys DesignWare PCIe IP and + thus inherits all the common properties defined in snps,dw-pcie-ep.yaml. + The controller instances are dual mode where in they can work either in + Root Port mode or Endpoint mode but one at a time. + +properties: + compatible: + enum: + - fsl,imx8mm-pcie-ep + - fsl,imx8mq-pcie-ep + - fsl,imx8mp-pcie-ep + + reg: + minItems: 2 + + reg-names: + items: + - const: dbi + - const: addr_space + + interrupts: + items: + - description: builtin eDMA interrupter. + + interrupt-names: + items: + - const: dma + + clocks: + minItems: 3 + items: + - description: PCIe bridge clock. + - description: PCIe bus clock. + - description: PCIe PHY clock. + - description: Additional required clock entry for imx6sx-pcie-ep, + imx8mq-pcie-ep. + + clock-names: + minItems: 3 + items: + - const: pcie + - const: pcie_bus + - enum: [ pcie_phy, pcie_aux ] + - enum: [ pcie_inbound_axi, pcie_aux ] + + num-lanes: + const: 1 + + fsl,imx7d-pcie-phy: + $ref: /schemas/types.yaml#/definitions/phandle + description: A phandle to an fsl,imx7d-pcie-phy node. Additional + required properties for imx7d-pcie-ep and imx8mq-pcie-ep. + + power-domains: + minItems: 1 + items: + - description: The phandle pointing to the DISPLAY domain for + imx6sx-pcie-ep, to PCIE_PHY power domain for imx7d-pcie-ep and + imx8mq-pcie-ep. + - description: The phandle pointing to the PCIE_PHY power domains + for imx6sx-pcie-ep. + + power-domain-names: + minItems: 1 + items: + - const: pcie + - const: pcie_phy + + resets: + minItems: 2 + maxItems: 3 + description: Phandles to PCIe-related reset lines exposed by SRC + IP block. Additional required by imx7d-pcie-ep and imx8mq-pcie-ep. + + reset-names: + minItems: 2 + maxItems: 3 + + fsl,tx-deemph-gen1: + description: Gen1 De-emphasis value (optional required). + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + + fsl,tx-deemph-gen2-3p5db: + description: Gen2 (3.5db) De-emphasis value (optional required). + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + + fsl,tx-deemph-gen2-6db: + description: Gen2 (6db) De-emphasis value (optional required). + $ref: /schemas/types.yaml#/definitions/uint32 + default: 20 + + fsl,tx-swing-full: + description: Gen2 TX SWING FULL value (optional required). + $ref: /schemas/types.yaml#/definitions/uint32 + default: 127 + + fsl,tx-swing-low: + description: TX launch amplitude swing_low value (optional required). + $ref: /schemas/types.yaml#/definitions/uint32 + default: 127 + + fsl,max-link-speed: + description: Specify PCI Gen for link capability (optional required). + Note that the IMX6 LVDS clock outputs do not meet gen2 jitter + requirements and thus for gen2 capability a gen2 compliant clock + generator should be used and configured. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3, 4] + default: 1 + + phys: + maxItems: 1 + + phy-names: + const: pcie-phy + + vpcie-supply: + description: Should specify the regulator in charge of PCIe port power. + The regulator will be enabled when initializing the PCIe host and + disabled either as part of the init process or when shutting down + the host (optional required). + + vph-supply: + description: Should specify the regulator in charge of VPH one of + the three PCIe PHY powers. This regulator can be supplied by both + 1.8v and 3.3v voltage supplies (optional required). + +required: + - compatible + - reg + - reg-names + - num-lanes + - interrupts + - interrupt-names + - clocks + - clock-names + +allOf: + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# + + - if: + properties: + compatible: + contains: + const: fsl,imx6sx-pcie-ep + then: + properties: + clock-names: + items: + - {} + - {} + - const: pcie_phy + - const: pcie_inbound_axi + power-domains: + minItems: 2 + power-domain-names: + minItems: 2 + - if: + properties: + compatible: + contains: + const: fsl,imx8mq-pcie-ep + then: + properties: + clock-names: + items: + - {} + - {} + - const: pcie_phy + - const: pcie_aux + - if: + properties: + compatible: + not: + contains: + enum: + - fsl,imx6sx-pcie-ep + - fsl,imx8mq-pcie-ep + then: + properties: + clocks: + maxItems: 3 + clock-names: + maxItems: 3 + + - if: + properties: + compatible: + contains: + enum: + - fsl,imx6q-pcie-ep + - fsl,imx6qp-pcie-ep + - fsl,imx7d-pcie-ep + then: + properties: + clock-names: + maxItems: 3 + contains: + const: pcie_phy + + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8mm-pcie-ep + - fsl,imx8mp-pcie-ep + then: + properties: + clock-names: + maxItems: 3 + contains: + const: pcie_aux + - if: + properties: + compatible: + contains: + enum: + - fsl,imx6q-pcie-ep + - fsl,imx6qp-pcie-ep + then: + properties: + power-domains: false + power-domain-names: false + + - if: + not: + properties: + compatible: + contains: + enum: + - fsl,imx6sx-pcie-ep + - fsl,imx6q-pcie-ep + - fsl,imx6qp-pcie-ep + then: + properties: + power-domains: + maxItems: 1 + power-domain-names: false + + - if: + properties: + compatible: + contains: + enum: + - fsl,imx6q-pcie-ep + - fsl,imx6sx-pcie-ep + - fsl,imx6qp-pcie-ep + - fsl,imx7d-pcie-ep + - fsl,imx8mq-pcie-ep + then: + properties: + resets: + minItems: 3 + reset-names: + items: + - const: pciephy + - const: apps + - const: turnoff + else: + properties: + resets: + maxItems: 2 + reset-names: + items: + - const: apps + - const: turnoff + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + pcie_ep: pcie-ep@33800000 { + compatible =3D "fsl,imx8mp-pcie-ep"; + reg =3D <0x33800000 0x000400000>, <0x18000000 0x08000000>; + reg-names =3D "dbi", "addr_space"; + clocks =3D <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_HSIO_AXI>, + <&clk IMX8MP_CLK_PCIE_ROOT>; + clock-names =3D "pcie", "pcie_bus", "pcie_aux"; + assigned-clocks =3D <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-rates =3D <10000000>; + assigned-clock-parents =3D <&clk IMX8MP_SYS_PLL2_50M>; + num-lanes =3D <1>; + interrupts =3D ; /* eDMA */ + interrupt-names =3D "dma"; + fsl,max-link-speed =3D <3>; + power-domains =3D <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; + resets =3D <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names =3D "apps", "turnoff"; + phys =3D <&pcie_phy>; + phy-names =3D "pcie-phy"; + num-ib-windows =3D <4>; + num-ob-windows =3D <4>; + status =3D "disabled"; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 5dce1c45f4d1..663a0d5960d8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15997,6 +15997,7 @@ M: Lucas Stach L: linux-pci@vger.kernel.org L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained +F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml F: drivers/pci/controller/dwc/*imx6* =20 --=20 2.34.1 From nobody Sat Sep 13 22:27:32 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A464BC54EAA for ; Mon, 30 Jan 2023 03:57:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235477AbjA3D5w (ORCPT ); Sun, 29 Jan 2023 22:57:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47336 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235345AbjA3D5i (ORCPT ); Sun, 29 Jan 2023 22:57:38 -0500 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 935D920D31; Sun, 29 Jan 2023 19:57:36 -0800 (PST) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 485311A1DE2; Mon, 30 Jan 2023 04:57:35 +0100 (CET) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 134401A1DE1; Mon, 30 Jan 2023 04:57:35 +0100 (CET) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 3C9F3183ABF0; Mon, 30 Jan 2023 11:57:33 +0800 (+08) From: Richard Zhu To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, l.stach@pengutronix.de, shawnguo@kernel.org, lorenzo.pieralisi@arm.com, peng.fan@nxp.com, marex@denx.de, marcel.ziswiler@toradex.com, tharvey@gateworks.com, frank.li@nxp.com Cc: hongxing.zhu@nxp.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com Subject: [PATCH v7 3/5] arm64: dts: Add i.MX8MM PCIe EP support Date: Mon, 30 Jan 2023 11:32:17 +0800 Message-Id: <1675049539-14976-4-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1675049539-14976-1-git-send-email-hongxing.zhu@nxp.com> References: <1675049539-14976-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add i.MX8MM PCIe EP support. Signed-off-by: Richard Zhu --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 24 +++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mm.dtsi index 31f4548f85cf..a9552867e547 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1315,6 +1315,30 @@ pcie0: pcie@33800000 { status =3D "disabled"; }; =20 + pcie0_ep: pcie-ep@33800000 { + compatible =3D "fsl,imx8mm-pcie-ep"; + reg =3D <0x33800000 0x400000>, + <0x18000000 0x8000000>; + reg-names =3D "dbi", "addr_space"; + num-lanes =3D <1>; + interrupts =3D ; + interrupt-names =3D "dma"; + fsl,max-link-speed =3D <2>; + clocks =3D <&clk IMX8MM_CLK_PCIE1_ROOT>, + <&clk IMX8MM_CLK_PCIE1_PHY>, + <&clk IMX8MM_CLK_PCIE1_AUX>; + clock-names =3D "pcie", "pcie_bus", "pcie_aux"; + power-domains =3D <&pgc_pcie>; + resets =3D <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names =3D "apps", "turnoff"; + phys =3D <&pcie_phy>; + phy-names =3D "pcie-phy"; + num-ib-windows =3D <4>; + num-ob-windows =3D <4>; + status =3D "disabled"; + }; + gpu_3d: gpu@38000000 { compatible =3D "vivante,gc"; reg =3D <0x38000000 0x8000>; --=20 2.34.1 From nobody Sat Sep 13 22:27:32 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55071C54EED for ; Mon, 30 Jan 2023 03:57:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235423AbjA3D5z (ORCPT ); Sun, 29 Jan 2023 22:57:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47304 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235443AbjA3D5j (ORCPT ); Sun, 29 Jan 2023 22:57:39 -0500 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E20FD1E1ED; Sun, 29 Jan 2023 19:57:37 -0800 (PST) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id A3E601A1DD7; Mon, 30 Jan 2023 04:57:36 +0100 (CET) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 6F3AA1A1DE1; Mon, 30 Jan 2023 04:57:36 +0100 (CET) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 9DC69180222F; Mon, 30 Jan 2023 11:57:34 +0800 (+08) From: Richard Zhu To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, l.stach@pengutronix.de, shawnguo@kernel.org, lorenzo.pieralisi@arm.com, peng.fan@nxp.com, marex@denx.de, marcel.ziswiler@toradex.com, tharvey@gateworks.com, frank.li@nxp.com Cc: hongxing.zhu@nxp.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com Subject: [PATCH v7 4/5] arm64: dts: Add i.MX8MQ PCIe EP support Date: Mon, 30 Jan 2023 11:32:18 +0800 Message-Id: <1675049539-14976-5-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1675049539-14976-1-git-send-email-hongxing.zhu@nxp.com> References: <1675049539-14976-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add i.MX8MQ PCIe EP support. Signed-off-by: Richard Zhu --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 32 +++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mq.dtsi index 98fbba4c99a9..9f950a6ac6c9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1605,6 +1605,38 @@ pcie1: pcie@33c00000 { status =3D "disabled"; }; =20 + pcie1_ep: pcie-ep@33c00000 { + compatible =3D "fsl,imx8mq-pcie-ep"; + reg =3D <0x33c00000 0x000400000>, + <0x20000000 0x08000000>; + reg-names =3D "dbi", "addr_space"; + num-lanes =3D <1>; + interrupts =3D ; + interrupt-names =3D "dma"; + fsl,max-link-speed =3D <2>; + clocks =3D <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&clk IMX8MQ_CLK_PCIE2_AUX>; + clock-names =3D "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; + power-domains =3D <&pgc_pcie>; + resets =3D <&src IMX8MQ_RESET_PCIEPHY2>, + <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; + reset-names =3D "pciephy", "apps", "turnoff"; + assigned-clocks =3D <&clk IMX8MQ_CLK_PCIE2_CTRL>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&clk IMX8MQ_CLK_PCIE2_AUX>; + assigned-clock-parents =3D <&clk IMX8MQ_SYS2_PLL_250M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS1_PLL_80M>; + assigned-clock-rates =3D <250000000>, <100000000>, + <10000000>; + num-ib-windows =3D <4>; + num-ob-windows =3D <4>; + status =3D "disabled"; + }; + gic: interrupt-controller@38800000 { compatible =3D "arm,gic-v3"; reg =3D <0x38800000 0x10000>, /* GIC Dist */ --=20 2.34.1 From nobody Sat Sep 13 22:27:32 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B728C54EED for ; Mon, 30 Jan 2023 03:58:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234378AbjA3D56 (ORCPT ); Sun, 29 Jan 2023 22:57:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47680 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235314AbjA3D5q (ORCPT ); Sun, 29 Jan 2023 22:57:46 -0500 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 546ED199D4; Sun, 29 Jan 2023 19:57:39 -0800 (PST) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 0BC5020087C; Mon, 30 Jan 2023 04:57:38 +0100 (CET) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id C7716200030; Mon, 30 Jan 2023 04:57:37 +0100 (CET) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 05F97183ABF0; Mon, 30 Jan 2023 11:57:35 +0800 (+08) From: Richard Zhu To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, l.stach@pengutronix.de, shawnguo@kernel.org, lorenzo.pieralisi@arm.com, peng.fan@nxp.com, marex@denx.de, marcel.ziswiler@toradex.com, tharvey@gateworks.com, frank.li@nxp.com Cc: hongxing.zhu@nxp.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com Subject: [PATCH v7 5/5] arm64: dts: Add i.MX8MP PCIe EP support Date: Mon, 30 Jan 2023 11:32:19 +0800 Message-Id: <1675049539-14976-6-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1675049539-14976-1-git-send-email-hongxing.zhu@nxp.com> References: <1675049539-14976-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add i.MX8MP PCIe EP support. Signed-off-by: Richard Zhu --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 26 +++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mp.dtsi index a19224fe1a6a..2f84b8b0118e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1309,6 +1309,32 @@ pcie: pcie@33800000 { status =3D "disabled"; }; =20 + pcie_ep: pcie-ep@33800000 { + compatible =3D "fsl,imx8mp-pcie-ep"; + reg =3D <0x33800000 0x000400000>, <0x18000000 0x08000000>; + reg-names =3D "dbi", "addr_space"; + clocks =3D <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_HSIO_AXI>, + <&clk IMX8MP_CLK_PCIE_ROOT>; + clock-names =3D "pcie", "pcie_bus", "pcie_aux"; + assigned-clocks =3D <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-rates =3D <10000000>; + assigned-clock-parents =3D <&clk IMX8MP_SYS_PLL2_50M>; + num-lanes =3D <1>; + interrupts =3D ; /* eDMA */ + interrupt-names =3D "dma"; + fsl,max-link-speed =3D <3>; + power-domains =3D <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; + resets =3D <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names =3D "apps", "turnoff"; + phys =3D <&pcie_phy>; + phy-names =3D "pcie-phy"; + num-ib-windows =3D <4>; + num-ob-windows =3D <4>; + status =3D "disabled"; + }; + gpu3d: gpu@38000000 { compatible =3D "vivante,gc"; reg =3D <0x38000000 0x8000>; --=20 2.34.1