From nobody Sun Apr 5 20:04:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7ACDBC54EBE for ; Fri, 13 Jan 2023 12:37:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241680AbjAMMhx (ORCPT ); Fri, 13 Jan 2023 07:37:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33718 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241198AbjAMMcV (ORCPT ); Fri, 13 Jan 2023 07:32:21 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 73D805790E; Fri, 13 Jan 2023 04:31:18 -0800 (PST) Date: Fri, 13 Jan 2023 12:31:16 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1673613077; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=pH+/AUjLMi0RkpNqY6kzxjvRNmvehdclKJlXaUA5dlk=; b=wemA1wEkyDn19OBTw/F4i/vK8OADykfoGFBDfW3xovebVm9NWaIySr1HFI0MjrFoItjv6x UKAb1F2uyaVvTI+uPkMhOmFNm7z8ugEi2uHW8vXMx85Qv0RC1EJAJEgEQS+MRICEtjWAMZ iyxEh0YE4ia+dQIgQTK3fyHTYCqmdYTOUa3x+iU/mZJjRpTPb17anC7x8FyxVvmGNq+Vtp MaTWC+x3B4P/vWtBnyxyIaA4OBGnOWJIJ5xgOJB/TzrEOmMHCPg1P90srWsuwGjWRir7t5 8Rtad3e/SkaYv4QDa/k9dhoeyR+KflwSBrrYBwpnPgUHdW4j1PA8V6kti52vFA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1673613077; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=pH+/AUjLMi0RkpNqY6kzxjvRNmvehdclKJlXaUA5dlk=; b=UABzBGKswv36SayMlmrvxCeFbO5yNE/yIDcgJcNBzJ28Uij292RLFpvLKseESsAKm9qsn7 UMBRPotrwv826BBQ== From: "tip-bot2 for Peter Zijlstra" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: sched/core] x86/perf/amd: Remove tracing from perf_lopwr_cb() Cc: "Peter Zijlstra (Intel)" , Ingo Molnar , Tony Lindgren , Ulf Hansson , "Rafael J. Wysocki" , Frederic Weisbecker , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20230112195539.392862891@infradead.org> References: <20230112195539.392862891@infradead.org> MIME-Version: 1.0 Message-ID: <167361307678.4906.7808954024859813192.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the sched/core branch of tip: Commit-ID: 1f7c232ee080f01ded1236685a357f8926e8c7d5 Gitweb: https://git.kernel.org/tip/1f7c232ee080f01ded1236685a357f892= 6e8c7d5 Author: Peter Zijlstra AuthorDate: Thu, 12 Jan 2023 20:43:15 +01:00 Committer: Ingo Molnar CommitterDate: Fri, 13 Jan 2023 11:03:21 +01:00 x86/perf/amd: Remove tracing from perf_lopwr_cb() The perf_lopwr_cb() function is called from the idle routines; there is no RCU there, we must not enter tracing. Use __always_inline, noidle annotations and existing no-trace methods. Signed-off-by: Peter Zijlstra (Intel) Signed-off-by: Ingo Molnar Tested-by: Tony Lindgren Tested-by: Ulf Hansson Acked-by: Rafael J. Wysocki Acked-by: Frederic Weisbecker Link: https://lore.kernel.org/r/20230112195539.392862891@infradead.org --- arch/x86/events/amd/brs.c | 13 +++++-------- arch/x86/include/asm/perf_event.h | 2 +- 2 files changed, 6 insertions(+), 9 deletions(-) diff --git a/arch/x86/events/amd/brs.c b/arch/x86/events/amd/brs.c index 58461fa..ed30871 100644 --- a/arch/x86/events/amd/brs.c +++ b/arch/x86/events/amd/brs.c @@ -41,18 +41,15 @@ static inline unsigned int brs_to(int idx) return MSR_AMD_SAMP_BR_FROM + 2 * idx + 1; } =20 -static inline void set_debug_extn_cfg(u64 val) +static __always_inline void set_debug_extn_cfg(u64 val) { /* bits[4:3] must always be set to 11b */ - wrmsrl(MSR_AMD_DBG_EXTN_CFG, val | 3ULL << 3); + __wrmsr(MSR_AMD_DBG_EXTN_CFG, val | 3ULL << 3, val >> 32); } =20 -static inline u64 get_debug_extn_cfg(void) +static __always_inline u64 get_debug_extn_cfg(void) { - u64 val; - - rdmsrl(MSR_AMD_DBG_EXTN_CFG, val); - return val; + return __rdmsr(MSR_AMD_DBG_EXTN_CFG); } =20 static bool __init amd_brs_detect(void) @@ -405,7 +402,7 @@ void amd_pmu_brs_sched_task(struct perf_event_pmu_conte= xt *pmu_ctx, bool sched_i * called from ACPI processor_idle.c or acpi_pad.c * with interrupts disabled */ -void perf_amd_brs_lopwr_cb(bool lopwr_in) +void noinstr perf_amd_brs_lopwr_cb(bool lopwr_in) { struct cpu_hw_events *cpuc =3D this_cpu_ptr(&cpu_hw_events); union amd_debug_extn_cfg cfg; diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_= event.h index 5d0f689..76e7924 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -578,7 +578,7 @@ extern void perf_amd_brs_lopwr_cb(bool lopwr_in); =20 DECLARE_STATIC_CALL(perf_lopwr_cb, perf_amd_brs_lopwr_cb); =20 -static inline void perf_lopwr_cb(bool lopwr_in) +static __always_inline void perf_lopwr_cb(bool lopwr_in) { static_call_mod(perf_lopwr_cb)(lopwr_in); }