From nobody Thu Nov 14 07:25:04 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A374BC54EBE for ; Tue, 10 Jan 2023 05:55:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230286AbjAJFzY (ORCPT ); Tue, 10 Jan 2023 00:55:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230057AbjAJFzK (ORCPT ); Tue, 10 Jan 2023 00:55:10 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A29BBF79 for ; Mon, 9 Jan 2023 21:55:08 -0800 (PST) X-UUID: 9f6fb424af964269aa55797f61c1e68d-20230110 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=s5/tOMASlrJlrpdGZBEiIUGnY/yMA8EeWTUgOk0cPbU=; b=JCSBlMIYEOkUjVnVIBGoSKm0ZAfp/jJOo7IkIy3urCgzMujPXuXXpCrCfN6tIXlNLSO3EwYa+QdZyaH3DZjudaytDiE6E++PEZGAv3XwLkeosoDMfQEiNSCaOV7wslSFvMea+W3LkNbaj+zRCw/fEB8NPWvFUuEhUYAmwxRXP1Q=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.17,REQID:ad08ba1a-51d1-4514-8e82-1eea4eca1f10,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:90 X-CID-INFO: VERSION:1.1.17,REQID:ad08ba1a-51d1-4514-8e82-1eea4eca1f10,IP:0,URL :0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:90 X-CID-META: VersionHash:543e81c,CLOUDID:b94c3154-dd49-462e-a4be-2143a3ddc739,B ulkID:230110135505UYOEYBJE,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OS I:0,OSA:0 X-CID-BVR: 0 X-UUID: 9f6fb424af964269aa55797f61c1e68d-20230110 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1215836764; Tue, 10 Jan 2023 13:55:02 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Tue, 10 Jan 2023 13:55:02 +0800 Received: from mszsdaap41.gcn.mediatek.inc (10.16.6.141) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Tue, 10 Jan 2023 13:55:01 +0800 From: To: , , , , , , , , CC: , , , , , Xinlei Lee Subject: [PATCH v2 3/3] drm/panel: boe-tv101wum-nl6: Fine tune the panel power sequence Date: Tue, 10 Jan 2023 13:54:53 +0800 Message-ID: <1673330093-6771-4-git-send-email-xinlei.lee@mediatek.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1673330093-6771-1-git-send-email-xinlei.lee@mediatek.com> References: <1673330093-6771-1-git-send-email-xinlei.lee@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xinlei Lee For "boe,tv105wum-nw0" this special panel, it is stipulated in the=20 panel spec that MIPI needs to keep the LP11 state before the=20 lcm_reset pin is pulled high. Signed-off-by: Xinlei Lee --- drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c b/drivers/gpu/d= rm/panel/panel-boe-tv101wum-nl6.c index f0093035f1ff..67df61de64ae 100644 --- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c +++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c @@ -36,6 +36,7 @@ struct panel_desc { const struct panel_init_cmd *init_cmds; unsigned int lanes; bool discharge_on_disable; + bool lp11_before_reset; }; =20 struct boe_panel { @@ -1261,6 +1262,10 @@ static int boe_panel_prepare(struct drm_panel *panel) =20 usleep_range(10000, 11000); =20 + if (boe->desc->lp11_before_reset) { + mipi_dsi_dcs_nop(boe->dsi); + usleep_range(1000, 2000); + } gpiod_set_value(boe->enable_gpio, 1); usleep_range(1000, 2000); gpiod_set_value(boe->enable_gpio, 0); @@ -1487,6 +1492,7 @@ static const struct panel_desc boe_tv105wum_nw0_desc = =3D { .mode_flags =3D MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_LPM, .init_cmds =3D boe_init_cmd, + .lp11_before_reset =3D true, }; =20 static int boe_panel_get_modes(struct drm_panel *panel, --=20 2.18.0