From nobody Wed Sep 17 16:03:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0ED71C4332F for ; Sat, 17 Dec 2022 18:57:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230127AbiLQS5I (ORCPT ); Sat, 17 Dec 2022 13:57:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40794 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229547AbiLQSzj (ORCPT ); Sat, 17 Dec 2022 13:55:39 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB56F10FCE; Sat, 17 Dec 2022 10:55:36 -0800 (PST) Date: Sat, 17 Dec 2022 18:55:31 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1671303331; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vDF7dkaY5EZbsec4d9xzD3Tbhi7qNgM8LVvK5CISJ0k=; b=GBxkaW6exUCD5T7hQrry/3BcQuxde1klWYx7cVngbj+yrLBZsSlGut8+tlRT9TD+8X4AWj 59qJ9w+b2hfsBmjhVrbtjf4nGzsegpQjmQbQCMGj9/URUXHhBH/m/4TxG/bqOjuuPXomYi 6qFigxDozTu2sOWLDFB+z0QJfEfU6dG1nDbRQ9tnusYrzRCHkQ3DSfm42ukj6TGIhd1+CD xMrCZj+Ltkr6BCwm1gE4jy75wHzWwOnmwmfyqqEyLZFq/dcwp/A31LHCV9Y72Itd5v32qO pNKYn0n2oGGIEr+q+BL2p2ldXoJ1XGvakGd6LPyG/ghQtUM/epXPli+D2Or5LQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1671303331; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vDF7dkaY5EZbsec4d9xzD3Tbhi7qNgM8LVvK5CISJ0k=; b=4DZlTtSK4xez74Kucw60zZLQpsjDANXrL0kohUbLGMFWdGmZlAft4C670xp2hwptL8ngBI rl2yVp0FxfIjwGCg== From: "tip-bot2 for Pasha Tatashin" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/mm] x86/mm: Remove P*D_PAGE_MASK and P*D_PAGE_SIZE macros Cc: Pasha Tatashin , Borislav Petkov , Anshuman Khandual , Mike Rapoport , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20220516185202.604654-1-tatashin@google.com> References: <20220516185202.604654-1-tatashin@google.com> MIME-Version: 1.0 Message-ID: <167130333142.4906.5415241751325099908.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the x86/mm branch of tip: Commit-ID: 82328227db8f0b9b5f77bb5afcd47e59d0e4d08f Gitweb: https://git.kernel.org/tip/82328227db8f0b9b5f77bb5afcd47e59d= 0e4d08f Author: Pasha Tatashin AuthorDate: Mon, 16 May 2022 18:52:02=20 Committer: Dave Hansen CommitterDate: Thu, 15 Dec 2022 10:37:27 -08:00 x86/mm: Remove P*D_PAGE_MASK and P*D_PAGE_SIZE macros Other architectures and the common mm/ use P*D_MASK, and P*D_SIZE. Remove the duplicated P*D_PAGE_MASK and P*D_PAGE_SIZE which are only used in x86/*. Signed-off-by: Pasha Tatashin Signed-off-by: Borislav Petkov Reviewed-by: Anshuman Khandual Acked-by: Mike Rapoport Link: https://lore.kernel.org/r/20220516185202.604654-1-tatashin@google.com --- arch/x86/include/asm/page_types.h | 12 +++--------- arch/x86/kernel/amd_gart_64.c | 2 +- arch/x86/kernel/head64.c | 2 +- arch/x86/mm/mem_encrypt_boot.S | 4 ++-- arch/x86/mm/mem_encrypt_identity.c | 18 +++++++++--------- arch/x86/mm/pat/set_memory.c | 6 +++--- arch/x86/mm/pti.c | 2 +- 7 files changed, 20 insertions(+), 26 deletions(-) diff --git a/arch/x86/include/asm/page_types.h b/arch/x86/include/asm/page_= types.h index a506a41..86bd431 100644 --- a/arch/x86/include/asm/page_types.h +++ b/arch/x86/include/asm/page_types.h @@ -11,20 +11,14 @@ #define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT) #define PAGE_MASK (~(PAGE_SIZE-1)) =20 -#define PMD_PAGE_SIZE (_AC(1, UL) << PMD_SHIFT) -#define PMD_PAGE_MASK (~(PMD_PAGE_SIZE-1)) - -#define PUD_PAGE_SIZE (_AC(1, UL) << PUD_SHIFT) -#define PUD_PAGE_MASK (~(PUD_PAGE_SIZE-1)) - #define __VIRTUAL_MASK ((1UL << __VIRTUAL_MASK_SHIFT) - 1) =20 -/* Cast *PAGE_MASK to a signed type so that it is sign-extended if +/* Cast P*D_MASK to a signed type so that it is sign-extended if virtual addresses are 32-bits but physical addresses are larger (ie, 32-bit PAE). */ #define PHYSICAL_PAGE_MASK (((signed long)PAGE_MASK) & __PHYSICAL_MASK) -#define PHYSICAL_PMD_PAGE_MASK (((signed long)PMD_PAGE_MASK) & __PHYSICAL_= MASK) -#define PHYSICAL_PUD_PAGE_MASK (((signed long)PUD_PAGE_MASK) & __PHYSICAL_= MASK) +#define PHYSICAL_PMD_PAGE_MASK (((signed long)PMD_MASK) & __PHYSICAL_MASK) +#define PHYSICAL_PUD_PAGE_MASK (((signed long)PUD_MASK) & __PHYSICAL_MASK) =20 #define HPAGE_SHIFT PMD_SHIFT #define HPAGE_SIZE (_AC(1,UL) << HPAGE_SHIFT) diff --git a/arch/x86/kernel/amd_gart_64.c b/arch/x86/kernel/amd_gart_64.c index 19a0207..56a917d 100644 --- a/arch/x86/kernel/amd_gart_64.c +++ b/arch/x86/kernel/amd_gart_64.c @@ -504,7 +504,7 @@ static __init unsigned long check_iommu_size(unsigned l= ong aper, u64 aper_size) } =20 a =3D aper + iommu_size; - iommu_size -=3D round_up(a, PMD_PAGE_SIZE) - a; + iommu_size -=3D round_up(a, PMD_SIZE) - a; =20 if (iommu_size < 64*1024*1024) { pr_warn("PCI-DMA: Warning: Small IOMMU %luMB." diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c index 6a3cfaf..387e4b1 100644 --- a/arch/x86/kernel/head64.c +++ b/arch/x86/kernel/head64.c @@ -203,7 +203,7 @@ unsigned long __head __startup_64(unsigned long physadd= r, load_delta =3D physaddr - (unsigned long)(_text - __START_KERNEL_map); =20 /* Is the address not 2M aligned? */ - if (load_delta & ~PMD_PAGE_MASK) + if (load_delta & ~PMD_MASK) for (;;); =20 /* Include the SME encryption mask in the fixup value */ diff --git a/arch/x86/mm/mem_encrypt_boot.S b/arch/x86/mm/mem_encrypt_boot.S index 9de3d90..e25288e 100644 --- a/arch/x86/mm/mem_encrypt_boot.S +++ b/arch/x86/mm/mem_encrypt_boot.S @@ -26,7 +26,7 @@ SYM_FUNC_START(sme_encrypt_execute) * RCX - virtual address of the encryption workarea, including: * - stack page (PAGE_SIZE) * - encryption routine page (PAGE_SIZE) - * - intermediate copy buffer (PMD_PAGE_SIZE) + * - intermediate copy buffer (PMD_SIZE) * R8 - physical address of the pagetables to use for encryption */ =20 @@ -123,7 +123,7 @@ SYM_FUNC_START(__enc_copy) wbinvd /* Invalidate any cache entries */ =20 /* Copy/encrypt up to 2MB at a time */ - movq $PMD_PAGE_SIZE, %r12 + movq $PMD_SIZE, %r12 1: cmpq %r12, %r9 jnb 2f diff --git a/arch/x86/mm/mem_encrypt_identity.c b/arch/x86/mm/mem_encrypt_i= dentity.c index f415498..88cccd6 100644 --- a/arch/x86/mm/mem_encrypt_identity.c +++ b/arch/x86/mm/mem_encrypt_identity.c @@ -93,7 +93,7 @@ struct sme_populate_pgd_data { * section is 2MB aligned to allow for simple pagetable setup using only * PMD entries (see vmlinux.lds.S). */ -static char sme_workarea[2 * PMD_PAGE_SIZE] __section(".init.scratch"); +static char sme_workarea[2 * PMD_SIZE] __section(".init.scratch"); =20 static char sme_cmdline_arg[] __initdata =3D "mem_encrypt"; static char sme_cmdline_on[] __initdata =3D "on"; @@ -198,8 +198,8 @@ static void __init __sme_map_range_pmd(struct sme_popul= ate_pgd_data *ppd) while (ppd->vaddr < ppd->vaddr_end) { sme_populate_pgd_large(ppd); =20 - ppd->vaddr +=3D PMD_PAGE_SIZE; - ppd->paddr +=3D PMD_PAGE_SIZE; + ppd->vaddr +=3D PMD_SIZE; + ppd->paddr +=3D PMD_SIZE; } } =20 @@ -225,11 +225,11 @@ static void __init __sme_map_range(struct sme_populat= e_pgd_data *ppd, vaddr_end =3D ppd->vaddr_end; =20 /* If start is not 2MB aligned, create PTE entries */ - ppd->vaddr_end =3D ALIGN(ppd->vaddr, PMD_PAGE_SIZE); + ppd->vaddr_end =3D ALIGN(ppd->vaddr, PMD_SIZE); __sme_map_range_pte(ppd); =20 /* Create PMD entries */ - ppd->vaddr_end =3D vaddr_end & PMD_PAGE_MASK; + ppd->vaddr_end =3D vaddr_end & PMD_MASK; __sme_map_range_pmd(ppd); =20 /* If end is not 2MB aligned, create PTE entries */ @@ -325,7 +325,7 @@ void __init sme_encrypt_kernel(struct boot_params *bp) =20 /* Physical addresses gives us the identity mapped virtual addresses */ kernel_start =3D __pa_symbol(_text); - kernel_end =3D ALIGN(__pa_symbol(_end), PMD_PAGE_SIZE); + kernel_end =3D ALIGN(__pa_symbol(_end), PMD_SIZE); kernel_len =3D kernel_end - kernel_start; =20 initrd_start =3D 0; @@ -355,12 +355,12 @@ void __init sme_encrypt_kernel(struct boot_params *bp) * executable encryption area size: * stack page (PAGE_SIZE) * encryption routine page (PAGE_SIZE) - * intermediate copy buffer (PMD_PAGE_SIZE) + * intermediate copy buffer (PMD_SIZE) * pagetable structures for the encryption of the kernel * pagetable structures for workarea (in case not currently mapped) */ execute_start =3D workarea_start; - execute_end =3D execute_start + (PAGE_SIZE * 2) + PMD_PAGE_SIZE; + execute_end =3D execute_start + (PAGE_SIZE * 2) + PMD_SIZE; execute_len =3D execute_end - execute_start; =20 /* @@ -383,7 +383,7 @@ void __init sme_encrypt_kernel(struct boot_params *bp) * before it is mapped. */ workarea_len =3D execute_len + pgtable_area_len; - workarea_end =3D ALIGN(workarea_start + workarea_len, PMD_PAGE_SIZE); + workarea_end =3D ALIGN(workarea_start + workarea_len, PMD_SIZE); =20 /* * Set the address to the start of where newly created pagetable diff --git a/arch/x86/mm/pat/set_memory.c b/arch/x86/mm/pat/set_memory.c index f275605..06eb891 100644 --- a/arch/x86/mm/pat/set_memory.c +++ b/arch/x86/mm/pat/set_memory.c @@ -743,11 +743,11 @@ phys_addr_t slow_virt_to_phys(void *__virt_addr) switch (level) { case PG_LEVEL_1G: phys_addr =3D (phys_addr_t)pud_pfn(*(pud_t *)pte) << PAGE_SHIFT; - offset =3D virt_addr & ~PUD_PAGE_MASK; + offset =3D virt_addr & ~PUD_MASK; break; case PG_LEVEL_2M: phys_addr =3D (phys_addr_t)pmd_pfn(*(pmd_t *)pte) << PAGE_SHIFT; - offset =3D virt_addr & ~PMD_PAGE_MASK; + offset =3D virt_addr & ~PMD_MASK; break; default: phys_addr =3D (phys_addr_t)pte_pfn(*pte) << PAGE_SHIFT; @@ -1037,7 +1037,7 @@ __split_large_page(struct cpa_data *cpa, pte_t *kpte,= unsigned long address, case PG_LEVEL_1G: ref_prot =3D pud_pgprot(*(pud_t *)kpte); ref_pfn =3D pud_pfn(*(pud_t *)kpte); - pfninc =3D PMD_PAGE_SIZE >> PAGE_SHIFT; + pfninc =3D PMD_SIZE >> PAGE_SHIFT; lpaddr =3D address & PUD_MASK; lpinc =3D PMD_SIZE; /* diff --git a/arch/x86/mm/pti.c b/arch/x86/mm/pti.c index ffe3b3a..78414c6 100644 --- a/arch/x86/mm/pti.c +++ b/arch/x86/mm/pti.c @@ -592,7 +592,7 @@ static void pti_set_kernel_image_nonglobal(void) * of the image. */ unsigned long start =3D PFN_ALIGN(_text); - unsigned long end =3D ALIGN((unsigned long)_end, PMD_PAGE_SIZE); + unsigned long end =3D ALIGN((unsigned long)_end, PMD_SIZE); =20 /* * This clears _PAGE_GLOBAL from the entire kernel image.