From nobody Wed Sep 17 19:27:35 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C33DC4332F for ; Fri, 16 Dec 2022 21:46:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229951AbiLPVp7 (ORCPT ); Fri, 16 Dec 2022 16:45:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33526 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229752AbiLPVpb (ORCPT ); Fri, 16 Dec 2022 16:45:31 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 63BD16BCA7; Fri, 16 Dec 2022 13:45:30 -0800 (PST) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2BGLIOPf027431; Fri, 16 Dec 2022 21:45:23 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=D8mQaUr11uzwiRfKn/NUkh8jxLn0rwEAYG1hxGjXyqk=; b=ckqi2hKmDJkYjMiuz4nNoXvliGyedTi8Tntwk9DXp5YmJFfq+ERKO7hiasZNyWmfFmaB gpCb8SzDi2ZB233LCzYmL1wSa0GvXGfbVHL0X9NGGqg35kfyCInC3vQJ9hfbHQVO0sUC cWLaSaOTHxQwntEE0e5p/n2M3iF70ZmBjduNTUA9HaUYlnnR7AaHYwqEzwFnnnXNbV3G vwhLNag6fexxujkPQEmm+3rRYwaRP6AndxUyVd6o4H5mHIFC8+Jl5UUh8VLrbM6F7hFG YPRmeHdIZAACN4gSeXQFF9VtoucLwhvxVFkI3fDKeMZpcCUxMB6eloMub9NbMslMYu74 Vg== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3mgvecrs70-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Dec 2022 21:45:22 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 2BGLjLn3027618 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Dec 2022 21:45:21 GMT Received: from khsieh-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 16 Dec 2022 13:45:20 -0800 From: Kuogee Hsieh To: , , , , , , , , , , , , , , CC: Kuogee Hsieh , , , , , Subject: [PATCH v15 5/5] drm/msm/dp: add support of max dp link rate Date: Fri, 16 Dec 2022 13:45:02 -0800 Message-ID: <1671227102-21717-6-git-send-email-quic_khsieh@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1671227102-21717-1-git-send-email-quic_khsieh@quicinc.com> References: <1671227102-21717-1-git-send-email-quic_khsieh@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ElunmeELkkPos7daNDzivSj92SK7LAgL X-Proofpoint-ORIG-GUID: ElunmeELkkPos7daNDzivSj92SK7LAgL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-16_14,2022-12-15_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 lowpriorityscore=0 phishscore=0 mlxlogscore=999 priorityscore=1501 bulkscore=0 suspectscore=0 malwarescore=0 mlxscore=0 clxscore=1015 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2212160194 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" By default, HBR2 (5.4G) is the max link rate be supported. This patch uses the actual limit specified by DT and removes the artificial limitation to 5.4 Gbps. Supporting HBR3 is a consequence of that. Changes in v2: -- add max link rate from dtsi Changes in v3: -- parser max_data_lanes and max_dp_link_rate from dp_out endpoint Changes in v4: -- delete unnecessary pr_err Changes in v5: -- split parser function into different patch Changes in v9: -- revised commit test Changes in v13: -- repalced "properity" with "property" Signed-off-by: Kuogee Hsieh Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_display.c | 4 ++++ drivers/gpu/drm/msm/dp/dp_panel.c | 7 ++++--- drivers/gpu/drm/msm/dp/dp_panel.h | 1 + 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index bfd0aef..edee550 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -390,6 +390,10 @@ static int dp_display_process_hpd_high(struct dp_displ= ay_private *dp) struct edid *edid; =20 dp->panel->max_dp_lanes =3D dp->parser->max_dp_lanes; + dp->panel->max_dp_link_rate =3D dp->parser->max_dp_link_rate; + + drm_dbg_dp(dp->drm_dev, "max_lanes=3D%d max_link_rate=3D%d\n", + dp->panel->max_dp_lanes, dp->panel->max_dp_link_rate); =20 rc =3D dp_panel_read_sink_caps(dp->panel, dp->dp_display.connector); if (rc) diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_= panel.c index 5149ceb..1800d89 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -75,12 +75,13 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel) link_info->rate =3D drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); link_info->num_lanes =3D dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; =20 + /* Limit data lanes from data-lanes of endpoint property of dtsi */ if (link_info->num_lanes > dp_panel->max_dp_lanes) link_info->num_lanes =3D dp_panel->max_dp_lanes; =20 - /* Limit support upto HBR2 until HBR3 support is added */ - if (link_info->rate >=3D (drm_dp_bw_code_to_link_rate(DP_LINK_BW_5_4))) - link_info->rate =3D drm_dp_bw_code_to_link_rate(DP_LINK_BW_5_4); + /* Limit link rate from link-frequencies of endpoint property of dtsi */ + if (link_info->rate > dp_panel->max_dp_link_rate) + link_info->rate =3D dp_panel->max_dp_link_rate; =20 drm_dbg_dp(panel->drm_dev, "version: %d.%d\n", major, minor); drm_dbg_dp(panel->drm_dev, "link_rate=3D%d\n", link_info->rate); diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_= panel.h index d861197a..f04d021 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -50,6 +50,7 @@ struct dp_panel { =20 u32 vic; u32 max_dp_lanes; + u32 max_dp_link_rate; =20 u32 max_bw_code; }; --=20 The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project