From nobody Thu Sep 18 04:19:26 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B336BC4332F for ; Fri, 9 Dec 2022 15:47:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229912AbiLIPr5 (ORCPT ); Fri, 9 Dec 2022 10:47:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35398 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230265AbiLIPr1 (ORCPT ); Fri, 9 Dec 2022 10:47:27 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B56A37FB2; Fri, 9 Dec 2022 07:47:26 -0800 (PST) Date: Fri, 09 Dec 2022 15:47:23 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1670600843; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Ugvbu8bCpnbC5DCNpRmOEBr77QelCxeP+aizsD30U6E=; b=oZChamJcEAwxolx+mBxIAccQGI9H/XacibJqyqzlI2QFP2AV47wVneBfoXS01SHbl6wZQp CtQQrW261XLC186KvFd6m4oAJNxEcRcE8cXGxwGmdCQzgtm74yKCPVS6QOxIRep1QneUBU byh4l1EuW9GV1VT3z8xCV5rIZfmJdAo+zGnQ1oncJKUNzXtSQ7cThCos6saQ5WpJ34c91j P97tOHyIG31StDKN5/C4b/z7PYAhqY3AJ/cbD7jAX2Ry2hAyv2+5JTLRmMU538qwt/9FQd mA2IIue/d+4UcA3npe6AnbQvUdJXLPpRe5w51xZcTH/vfdbE0wUv1V8LOZYEOQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1670600843; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Ugvbu8bCpnbC5DCNpRmOEBr77QelCxeP+aizsD30U6E=; b=yg81HsiaPMRRzk2LrPmlso7UOy7PcCnQK62Z0bnt8CmsDsY9MHCd942/cJj2x6nnaZo9uR 7yrMnJF+/kDp/9AQ== From: tip-bot2 for Jonathan =?utf-8?q?Neusch=C3=A4fer?= Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: timers/core] clocksource/drivers/timer-npcm7xx: Enable timer 1 clock before use Cc: j.neuschaefer@gmx.net, Joel Stanley , Daniel Lezcano , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20221104161850.2889894-3-j.neuschaefer@gmx.net> References: <20221104161850.2889894-3-j.neuschaefer@gmx.net> MIME-Version: 1.0 Message-ID: <167060084346.4906.1652754113589535961.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the timers/core branch of tip: Commit-ID: db78539fc95cf62b0b8f274368fcd8202eac91f9 Gitweb: https://git.kernel.org/tip/db78539fc95cf62b0b8f274368fcd8202= eac91f9 Author: Jonathan Neusch=C3=A4fer AuthorDate: Fri, 04 Nov 2022 17:18:46 +01:00 Committer: Daniel Lezcano CommitterDate: Fri, 02 Dec 2022 12:48:28 +01:00 clocksource/drivers/timer-npcm7xx: Enable timer 1 clock before use In the WPCM450 SoC, the clocks for each timer can be gated individually. To prevent the timer 1 clock from being gated, enable it explicitly. Signed-off-by: Jonathan Neusch=C3=A4fer Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20221104161850.2889894-3-j.neuschaefer@gmx.= net Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-npcm7xx.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clocksource/timer-npcm7xx.c b/drivers/clocksource/time= r-npcm7xx.c index a00520c..9af30af 100644 --- a/drivers/clocksource/timer-npcm7xx.c +++ b/drivers/clocksource/timer-npcm7xx.c @@ -188,6 +188,7 @@ static void __init npcm7xx_clocksource_init(void) =20 static int __init npcm7xx_timer_init(struct device_node *np) { + struct clk *clk; int ret; =20 ret =3D timer_of_init(np, &npcm7xx_to); @@ -199,6 +200,15 @@ static int __init npcm7xx_timer_init(struct device_nod= e *np) npcm7xx_to.of_clk.rate =3D npcm7xx_to.of_clk.rate / (NPCM7XX_Tx_MIN_PRESCALE + 1); =20 + /* Enable the clock for timer1, if it exists */ + clk =3D of_clk_get(np, 1); + if (clk) { + if (!IS_ERR(clk)) + clk_prepare_enable(clk); + else + pr_warn("%pOF: Failed to get clock for timer1: %pe", np, clk); + } + npcm7xx_clocksource_init(); npcm7xx_clockevents_init(); =20