From nobody Thu Sep 18 14:13:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3D29C4321E for ; Mon, 5 Dec 2022 21:42:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233857AbiLEVmI (ORCPT ); Mon, 5 Dec 2022 16:42:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40942 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233742AbiLEVlu (ORCPT ); Mon, 5 Dec 2022 16:41:50 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9B0B22CCB9; Mon, 5 Dec 2022 13:41:48 -0800 (PST) Date: Mon, 05 Dec 2022 21:41:46 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1670276507; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xemZrY8VvbFDpZkx2nsw8iOahizDN/r13dIQFo1Gd6U=; b=CAESZvzAL9MGvdiksyituk+t0hCiqz/8WBtSOGRECjSDmj+7d7m314OowR0/XivJUNnNIl ZhvisdldFhlcseBPLsO0YFAzC7UazuzB3WjPfpINcjRcY4Pqo+gf0kyJdHuM9w1lpw0HYu DuwALM6/3Ax39/9sy8fLooW7E5XC/XCb5JWTneVMtuWyixyUaWPTDq+GyX62W+9SCJWW+x 9ArZzkNOF+0JkalUGetA+7AKQ3j64A8HvM2JnovZZ61OpX3aKaCVnOmnewaUaHAnKBD1Nx nThkw25aGixM6I95ZoFX4mxIkSe642nhLr92wx7nUbre7BxCCCjSe+sqtZLKPg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1670276507; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xemZrY8VvbFDpZkx2nsw8iOahizDN/r13dIQFo1Gd6U=; b=f5BJ8aTA/AWv0szLeqDz5VC/uP8KTjlwhps2Pxpic8llgfVO7ned44ap5r7PKelXZ8wB+y CKBBtRgAo9gUjrDQ== From: "tip-bot2 for Thomas Gleixner" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/core] iommu/amd: Enable PCI/IMS Cc: Thomas Gleixner , Kevin Tian , Marc Zyngier , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20221124232327.140571546@linutronix.de> References: <20221124232327.140571546@linutronix.de> MIME-Version: 1.0 Message-ID: <167027650647.4906.4169983710196863807.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the irq/core branch of tip: Commit-ID: fa5745aca1dc819aee6463a2475b5c277f7cf8f6 Gitweb: https://git.kernel.org/tip/fa5745aca1dc819aee6463a2475b5c277= f7cf8f6 Author: Thomas Gleixner AuthorDate: Fri, 25 Nov 2022 00:26:36 +01:00 Committer: Thomas Gleixner CommitterDate: Mon, 05 Dec 2022 22:22:35 +01:00 iommu/amd: Enable PCI/IMS PCI/IMS works like PCI/MSI-X in the remapping. Just add the feature flag, but only when on real hardware. Virtualized IOMMUs need additional support. Signed-off-by: Thomas Gleixner Reviewed-by: Kevin Tian Acked-by: Marc Zyngier Link: https://lore.kernel.org/r/20221124232327.140571546@linutronix.de --- drivers/iommu/amd/iommu.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 7caccd8..4d28967 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3649,11 +3649,20 @@ static struct irq_chip amd_ir_chip =3D { }; =20 static const struct msi_parent_ops amdvi_msi_parent_ops =3D { - .supported_flags =3D X86_VECTOR_MSI_FLAGS_SUPPORTED | MSI_FLAG_MULTI_PCI_= MSI, + .supported_flags =3D X86_VECTOR_MSI_FLAGS_SUPPORTED | + MSI_FLAG_MULTI_PCI_MSI | + MSI_FLAG_PCI_IMS, .prefix =3D "IR-", .init_dev_msi_info =3D msi_parent_init_dev_msi_info, }; =20 +static const struct msi_parent_ops virt_amdvi_msi_parent_ops =3D { + .supported_flags =3D X86_VECTOR_MSI_FLAGS_SUPPORTED | + MSI_FLAG_MULTI_PCI_MSI, + .prefix =3D "vIR-", + .init_dev_msi_info =3D msi_parent_init_dev_msi_info, +}; + int amd_iommu_create_irq_domain(struct amd_iommu *iommu) { struct fwnode_handle *fn; @@ -3670,7 +3679,11 @@ int amd_iommu_create_irq_domain(struct amd_iommu *io= mmu) =20 irq_domain_update_bus_token(iommu->ir_domain, DOMAIN_BUS_AMDVI); iommu->ir_domain->flags |=3D IRQ_DOMAIN_FLAG_MSI_PARENT; - iommu->ir_domain->msi_parent_ops =3D &amdvi_msi_parent_ops; + + if (amd_iommu_np_cache) + iommu->ir_domain->msi_parent_ops =3D &virt_amdvi_msi_parent_ops; + else + iommu->ir_domain->msi_parent_ops =3D &amdvi_msi_parent_ops; =20 return 0; }