From nobody Mon Apr 13 14:11:17 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 174EEC4332F for ; Mon, 5 Dec 2022 20:53:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232941AbiLEUx3 (ORCPT ); Mon, 5 Dec 2022 15:53:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232120AbiLEUx1 (ORCPT ); Mon, 5 Dec 2022 15:53:27 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9FE48B1FD; Mon, 5 Dec 2022 12:53:25 -0800 (PST) Date: Mon, 05 Dec 2022 20:53:22 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1670273603; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=CmsGGjpzr0dBe6axNex6kpBFOEjvbolY0Nmn4TPRCvc=; b=JMAgtz+xhtBoishR8oGm3vgwgwuOoQb+DlLCKFJZB0lHHt88mZTH/xoHVSHO/EFBgkOjO2 LWr6PgPEm/BBqYTA42St/ZGKfBSJqFdvLSlVkju84Q2EqyKNsCcr1oPpUEPEl1fVOgeyBN R2N0sJUYg9jQHSwwNzJo/CBe/kV4Lgn4fnHFuR+ew/zrwgceAr+mgtIjtfvhLWWdpl75Vu GlttJUThATB1buCJpF0o4j7bHtYQZHhn7bk9fKG4bzBJHz53NnIpj7P1/3b8o1oNp24aZK TgISUl/2p82DkFVzwQiY+MrPVk1uFBpF2a3U+Dl8qJFojOg3l9Z5wTJ01eKUzQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1670273603; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=CmsGGjpzr0dBe6axNex6kpBFOEjvbolY0Nmn4TPRCvc=; b=eZF06C9aemDd9Np90Kk0EQVhbC0Drqzoj+mOTbK+IKQy+qsMBjxJBXW6a8NvS6+N0rD2Qt cK6hMdYbqNO4C1DQ== From: "tip-bot2 for Ashok Raj" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/microcode] x86/microcode/intel: Do not retry microcode reloading on the APs Cc: Ashok Raj , "Borislav Petkov (AMD)" , Thomas Gleixner , stable@vger.kernel.org, x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20221129210832.107850-3-ashok.raj@intel.com> References: <20221129210832.107850-3-ashok.raj@intel.com> MIME-Version: 1.0 Message-ID: <167027360301.4906.8791952647948114025.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the x86/microcode branch of tip: Commit-ID: be1b670f61443aa5d0d01782e9b8ea0ee825d018 Gitweb: https://git.kernel.org/tip/be1b670f61443aa5d0d01782e9b8ea0ee= 825d018 Author: Ashok Raj AuthorDate: Tue, 29 Nov 2022 13:08:27 -08:00 Committer: Borislav Petkov (AMD) CommitterDate: Mon, 05 Dec 2022 21:22:21 +01:00 x86/microcode/intel: Do not retry microcode reloading on the APs The retries in load_ucode_intel_ap() were in place to support systems with mixed steppings. Mixed steppings are no longer supported and there is only one microcode image at a time. Any retries will simply reattempt to apply the same image over and over without making progress. [ bp: Zap the circumstantial reasoning from the commit message. ] Fixes: 06b8534cb728 ("x86/microcode: Rework microcode loading") Signed-off-by: Ashok Raj Signed-off-by: Borislav Petkov (AMD) Reviewed-by: Thomas Gleixner Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20221129210832.107850-3-ashok.raj@intel.com --- arch/x86/kernel/cpu/microcode/intel.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index 4f93875..2dba4b5 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -495,7 +495,6 @@ void load_ucode_intel_ap(void) else iup =3D &intel_ucode_patch; =20 -reget: if (!*iup) { patch =3D __load_ucode_intel(&uci); if (!patch) @@ -506,12 +505,7 @@ reget: =20 uci.mc =3D *iup; =20 - if (apply_microcode_early(&uci, true)) { - /* Mixed-silicon system? Try to refetch the proper patch: */ - *iup =3D NULL; - - goto reget; - } + apply_microcode_early(&uci, true); } =20 static struct microcode_intel *find_patch(struct ucode_cpu_info *uci)