From nobody Thu Sep 18 14:13:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BDA9BC4332F for ; Mon, 5 Dec 2022 18:25:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232774AbiLESZ1 (ORCPT ); Mon, 5 Dec 2022 13:25:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39456 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232284AbiLESZO (ORCPT ); Mon, 5 Dec 2022 13:25:14 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DF2A3209AE; Mon, 5 Dec 2022 10:25:12 -0800 (PST) Date: Mon, 05 Dec 2022 18:25:10 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1670264710; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=k5wGbLfHqr1nnSCyA5sXrLPy2oxdZCa8YH5qCdyQ1sc=; b=VsdEpw7QEubc634gEgU0QzWxeJmvPBUV375L406qrO7OWthTQ/YnBXNjcEAihLP7rY/4So BjRvZeFxLoyIv7npkE+DXBIqixz1tzqI1qFFrnn03JSg9mUlp0SYxLJihRca3igPnTWDlN gQe0JhqH5+Pm6Fro3hC84kVpJdyvpRBNZQr+o9Jdg3rMbhFvVksrB3edIMcWdQuT4HbB2e sdaoTV+a2K97G0ir6CHohca5oG1tCFfizFe5Ux/vHlVVQJUB3mFdseAyh1dBfiOq6EKSIV T2R2REWMYmeETzN2oHW/aIrmCa233hSoeEVyfd8uL6lp1gZH3YiJcIUaV2e9vA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1670264710; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=k5wGbLfHqr1nnSCyA5sXrLPy2oxdZCa8YH5qCdyQ1sc=; b=ab8V/6eVP68gBrnF+0SPtujoPk0eijMcrVYUPkd1rBy7Rw/P2gwmQmWPnN+0mqi4TC2T9v VvrREKCFM4tnEPCg== From: "tip-bot2 for Thomas Gleixner" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/core] iommu/amd: Enable PCI/IMS Cc: Thomas Gleixner , Kevin Tian , Marc Zyngier , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20221124232327.140571546@linutronix.de> References: <20221124232327.140571546@linutronix.de> MIME-Version: 1.0 Message-ID: <167026471013.4906.1375739872985314530.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the irq/core branch of tip: Commit-ID: 73c658f384d7a48e0e18ef0bc5458c8c6ea80574 Gitweb: https://git.kernel.org/tip/73c658f384d7a48e0e18ef0bc5458c8c6= ea80574 Author: Thomas Gleixner AuthorDate: Fri, 25 Nov 2022 00:26:36 +01:00 Committer: Thomas Gleixner CommitterDate: Mon, 05 Dec 2022 19:21:05 +01:00 iommu/amd: Enable PCI/IMS PCI/IMS works like PCI/MSI-X in the remapping. Just add the feature flag, but only when on real hardware. Virtualized IOMMUs need additional support. Signed-off-by: Thomas Gleixner Reviewed-by: Kevin Tian Acked-by: Marc Zyngier Link: https://lore.kernel.org/r/20221124232327.140571546@linutronix.de --- drivers/iommu/amd/iommu.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 7caccd8..4d28967 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3649,11 +3649,20 @@ static struct irq_chip amd_ir_chip =3D { }; =20 static const struct msi_parent_ops amdvi_msi_parent_ops =3D { - .supported_flags =3D X86_VECTOR_MSI_FLAGS_SUPPORTED | MSI_FLAG_MULTI_PCI_= MSI, + .supported_flags =3D X86_VECTOR_MSI_FLAGS_SUPPORTED | + MSI_FLAG_MULTI_PCI_MSI | + MSI_FLAG_PCI_IMS, .prefix =3D "IR-", .init_dev_msi_info =3D msi_parent_init_dev_msi_info, }; =20 +static const struct msi_parent_ops virt_amdvi_msi_parent_ops =3D { + .supported_flags =3D X86_VECTOR_MSI_FLAGS_SUPPORTED | + MSI_FLAG_MULTI_PCI_MSI, + .prefix =3D "vIR-", + .init_dev_msi_info =3D msi_parent_init_dev_msi_info, +}; + int amd_iommu_create_irq_domain(struct amd_iommu *iommu) { struct fwnode_handle *fn; @@ -3670,7 +3679,11 @@ int amd_iommu_create_irq_domain(struct amd_iommu *io= mmu) =20 irq_domain_update_bus_token(iommu->ir_domain, DOMAIN_BUS_AMDVI); iommu->ir_domain->flags |=3D IRQ_DOMAIN_FLAG_MSI_PARENT; - iommu->ir_domain->msi_parent_ops =3D &amdvi_msi_parent_ops; + + if (amd_iommu_np_cache) + iommu->ir_domain->msi_parent_ops =3D &virt_amdvi_msi_parent_ops; + else + iommu->ir_domain->msi_parent_ops =3D &amdvi_msi_parent_ops; =20 return 0; }