From nobody Thu Apr 16 09:12:26 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C054C43217 for ; Mon, 28 Nov 2022 11:54:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231314AbiK1LyK (ORCPT ); Mon, 28 Nov 2022 06:54:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59264 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231254AbiK1Lx6 (ORCPT ); Mon, 28 Nov 2022 06:53:58 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB45E272 for ; Mon, 28 Nov 2022 03:53:57 -0800 (PST) Date: Mon, 28 Nov 2022 11:53:55 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1669636436; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=OsT3JBv1TvycJpzHfUmTRaWZWrTkCfAGZLlzW1Omgng=; b=YwRvENovCte4EfJxXhwF91xuRViphsipEN+cjcCTv3jtrhcWwPczNKbQlHXsBMD4o+nfdW ROsYe6ghRRfzN7qmU466PZ549AF23kwN9ICu2xIijxM0HsiSSUG7Z3OGZ18rE0mJT1ORj8 bc3sZB4hDzwZbzOJhgcGqT7q5tCNaEEgOGPzOyTR57N0U2Lz5EKjOTXsf6LLz5SZoO3bBE cF/v3/2gmjAj/bqEmY9bcxW4fs2bZErRaLOLYXAAYd1lliIGAew89ydHrYXGqPwlg2o/86 foaKAp2EVBcCRgFr8LjcMB049p13R6U3wsParjdYLCkrhStligWQnN1aBENKaQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1669636436; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=OsT3JBv1TvycJpzHfUmTRaWZWrTkCfAGZLlzW1Omgng=; b=+DG5ngDsL8vbCkOynYS/RvBm4F/F3+qwYSi8KTY39FF7bRMMBMoXDKgr9HqIQrkRKuzydC v+CHHhbydi6lMGAA== From: "irqchip-bot for AngeloGioacchino Del Regno" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-kernel@vger.kernel.org Subject: [irqchip: irq/irqchip-next] irqchip/irq-mtk-cirq: Move register offsets to const array Cc: AngeloGioacchino Del Regno , Marc Zyngier , tglx@linutronix.de In-Reply-To: <20221128092217.36552-4-angelogioacchino.delregno@collabora.com> References: <20221128092217.36552-4-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Message-ID: <166963643518.4906.3785465592232185237.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the irq/irqchip-next branch of ir= qchip: Commit-ID: 45ac01959edcecfa5d6652c2397d3866e55b0da8 Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-plat= forms/45ac01959edcecfa5d6652c2397d3866e55b0da8 Author: AngeloGioacchino Del Regno AuthorDate: Mon, 28 Nov 2022 10:22:16 +01:00 Committer: Marc Zyngier CommitterDate: Mon, 28 Nov 2022 11:43:56=20 irqchip/irq-mtk-cirq: Move register offsets to const array In preparation to add support for new SoCs having a different register layout, add an enumeration that documents register offsets and move the definitions for the same to a u32 array; Selecting the right register offsets array is done by adding an of_device_id array containing all of the currently supported compatible strings pointing to the "v1" offsets array (as data): since no devicetree declares the `mediatek,mtk-cirq` compatible without a SoC-specific one, it wasn't necessary to provide any legacy fallback. Every usage of the aforemementioned definitions was changed to get a register address through a newly introduced `mtk_cirq_reg()` accessor. This change brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20221128092217.36552-4-angelogioacchino.del= regno@collabora.com --- drivers/irqchip/irq-mtk-cirq.c | 82 ++++++++++++++++++++++++++------- 1 file changed, 65 insertions(+), 17 deletions(-) diff --git a/drivers/irqchip/irq-mtk-cirq.c b/drivers/irqchip/irq-mtk-cirq.c index 9bca091..4776ed6 100644 --- a/drivers/irqchip/irq-mtk-cirq.c +++ b/drivers/irqchip/irq-mtk-cirq.c @@ -15,14 +15,29 @@ #include #include =20 -#define CIRQ_ACK 0x40 -#define CIRQ_MASK_SET 0xc0 -#define CIRQ_MASK_CLR 0x100 -#define CIRQ_SENS_SET 0x180 -#define CIRQ_SENS_CLR 0x1c0 -#define CIRQ_POL_SET 0x240 -#define CIRQ_POL_CLR 0x280 -#define CIRQ_CONTROL 0x300 +enum mtk_cirq_regoffs_index { + CIRQ_STA, + CIRQ_ACK, + CIRQ_MASK_SET, + CIRQ_MASK_CLR, + CIRQ_SENS_SET, + CIRQ_SENS_CLR, + CIRQ_POL_SET, + CIRQ_POL_CLR, + CIRQ_CONTROL +}; + +static const u32 mtk_cirq_regoffs_v1[] =3D { + [CIRQ_STA] =3D 0x0, + [CIRQ_ACK] =3D 0x40, + [CIRQ_MASK_SET] =3D 0xc0, + [CIRQ_MASK_CLR] =3D 0x100, + [CIRQ_SENS_SET] =3D 0x180, + [CIRQ_SENS_CLR] =3D 0x1c0, + [CIRQ_POL_SET] =3D 0x240, + [CIRQ_POL_CLR] =3D 0x280, + [CIRQ_CONTROL] =3D 0x300, +}; =20 #define CIRQ_EN 0x1 #define CIRQ_EDGE 0x2 @@ -32,18 +47,32 @@ struct mtk_cirq_chip_data { void __iomem *base; unsigned int ext_irq_start; unsigned int ext_irq_end; + const u32 *offsets; struct irq_domain *domain; }; =20 static struct mtk_cirq_chip_data *cirq_data; =20 -static void mtk_cirq_write_mask(struct irq_data *data, unsigned int offset) +static void __iomem *mtk_cirq_reg(struct mtk_cirq_chip_data *chip_data, + enum mtk_cirq_regoffs_index idx) +{ + return chip_data->base + chip_data->offsets[idx]; +} + +static void __iomem *mtk_cirq_irq_reg(struct mtk_cirq_chip_data *chip_data, + enum mtk_cirq_regoffs_index idx, + unsigned int cirq_num) +{ + return mtk_cirq_reg(chip_data, idx) + (cirq_num / 32) * 4; +} + +static void mtk_cirq_write_mask(struct irq_data *data, enum mtk_cirq_regof= fs_index idx) { struct mtk_cirq_chip_data *chip_data =3D data->chip_data; unsigned int cirq_num =3D data->hwirq; u32 mask =3D 1 << (cirq_num % 32); =20 - writel_relaxed(mask, chip_data->base + offset + (cirq_num / 32) * 4); + writel_relaxed(mask, mtk_cirq_irq_reg(chip_data, idx, cirq_num)); } =20 static void mtk_cirq_mask(struct irq_data *data) @@ -160,6 +189,7 @@ static const struct irq_domain_ops cirq_domain_ops =3D { #ifdef CONFIG_PM_SLEEP static int mtk_cirq_suspend(void) { + void __iomem *reg; u32 value, mask; unsigned int irq, hwirq_num; bool pending, masked; @@ -200,31 +230,34 @@ static int mtk_cirq_suspend(void) continue; } =20 + reg =3D mtk_cirq_irq_reg(cirq_data, CIRQ_ACK, i); mask =3D 1 << (i % 32); - writel_relaxed(mask, cirq_data->base + CIRQ_ACK + (i / 32) * 4); + writel_relaxed(mask, reg); } =20 /* set edge_only mode, record edge-triggerd interrupts */ /* enable cirq */ - value =3D readl_relaxed(cirq_data->base + CIRQ_CONTROL); + reg =3D mtk_cirq_reg(cirq_data, CIRQ_CONTROL); + value =3D readl_relaxed(reg); value |=3D (CIRQ_EDGE | CIRQ_EN); - writel_relaxed(value, cirq_data->base + CIRQ_CONTROL); + writel_relaxed(value, reg); =20 return 0; } =20 static void mtk_cirq_resume(void) { + void __iomem *reg =3D mtk_cirq_reg(cirq_data, CIRQ_CONTROL); u32 value; =20 /* flush recorded interrupts, will send signals to parent controller */ - value =3D readl_relaxed(cirq_data->base + CIRQ_CONTROL); - writel_relaxed(value | CIRQ_FLUSH, cirq_data->base + CIRQ_CONTROL); + value =3D readl_relaxed(reg); + writel_relaxed(value | CIRQ_FLUSH, reg); =20 /* disable cirq */ - value =3D readl_relaxed(cirq_data->base + CIRQ_CONTROL); + value =3D readl_relaxed(reg); value &=3D ~(CIRQ_EDGE | CIRQ_EN); - writel_relaxed(value, cirq_data->base + CIRQ_CONTROL); + writel_relaxed(value, reg); } =20 static struct syscore_ops mtk_cirq_syscore_ops =3D { @@ -240,10 +273,18 @@ static void mtk_cirq_syscore_init(void) static inline void mtk_cirq_syscore_init(void) {} #endif =20 +static const struct of_device_id mtk_cirq_of_match[] =3D { + { .compatible =3D "mediatek,mt2701-cirq", .data =3D &mtk_cirq_regoffs_v1 = }, + { .compatible =3D "mediatek,mt8135-cirq", .data =3D &mtk_cirq_regoffs_v1 = }, + { .compatible =3D "mediatek,mt8173-cirq", .data =3D &mtk_cirq_regoffs_v1 = }, + { /* sentinel */ } +}; + static int __init mtk_cirq_of_init(struct device_node *node, struct device_node *parent) { struct irq_domain *domain, *domain_parent; + const struct of_device_id *match; unsigned int irq_num; int ret; =20 @@ -274,6 +315,13 @@ static int __init mtk_cirq_of_init(struct device_node = *node, if (ret) goto out_unmap; =20 + match =3D of_match_node(mtk_cirq_of_match, node); + if (!match) { + ret =3D -ENODEV; + goto out_unmap; + } + cirq_data->offsets =3D match->data; + irq_num =3D cirq_data->ext_irq_end - cirq_data->ext_irq_start + 1; domain =3D irq_domain_add_hierarchy(domain_parent, 0, irq_num, node,