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Wed, 9 Nov 2022 06:20:23 -0800 From: Kartik To: , , , , , , , , , , , Subject: [PATCH v3] soc/tegra: fuse: use platform info with soc revision Date: Wed, 9 Nov 2022 19:50:22 +0530 Message-ID: <1668003622-13706-1-git-send-email-kkartik@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT101:EE_|DS7PR12MB6167:EE_ X-MS-Office365-Filtering-Correlation-Id: c4af4b1f-92c6-4d27-9427-08dac25d93a3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: VJ9mjtfsi159f72SI5sWVgBgmL2SDaWx9qYBIvf3iVFrCak0lnXMpK2DsMLtotOdpWIXasLjL4yOeqRcYf5r0d715YyWUJM8WhOlAaAlfaE1MT2dUOwVICnZwPTqCEXT5kf8xG0nzM/iAovsdYU4GWORYChkfDryfkYR5gQjPeja8H3/VY3oop8+Jhfx5qh8KhwgO0c7QJIl9Uurhc9e/fvK6MvCq757wAdM5xAgEPTKEA5QbTfgSJRH8z3jJeTv00c+gHZ1Cbo7a61bwGrHLQ3f2Kgm/oPM4pKsMDBdZSX690oiMhgVls1P5xZH7k3tYY7PduYE54kKU/GW7kH76UP00+629594sc03Ll7T83tlkm7qAPLZkjkPe0zKWKi5GKLQd3zcVFLJ+RomMJCEC+eJ+HVy+3fUQVLIiJ1XEVTObZmYYPgywUd8WMOwvd06j5Z2Yvu3o310BZgh65Ik8nwjDVETFTvW3l+sWbs5vOqROkjX84MlOJWpcgWc7Vn0D2zf++ohVBOP2nmfpyY2F7eHikLoF4OfTnZp+0PYQCIkxEUC26KEmGugKr7VeUgyjDRI1zhZz1yaPzx94rBzE865cyiGQPCehldTivgY1VcNbkimdxhQpimT6D6WumksGXtIlj+7dk/H50hc8pC3dMU7Lu7WPBlRP/rpE+CkNAlFu/ozG+bHsnScjiKDuqo/Rlyp4vr89Vyok6VIF4KwAEG252ryU5rsaPDdSpOhLMaorsm0nu6Drv6PQZp84Vi14tjUy01j00NbnzDLFg4us4dxJ10idgNGPHZwUk5sGEo= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(396003)(39860400002)(376002)(346002)(136003)(451199015)(40470700004)(36840700001)(46966006)(82740400003)(36860700001)(86362001)(82310400005)(921005)(478600001)(8936002)(26005)(40460700003)(70206006)(110136005)(2906002)(316002)(83380400001)(5660300002)(186003)(336012)(70586007)(41300700001)(2616005)(8676002)(356005)(47076005)(7636003)(426003)(7696005)(36756003)(40480700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2022 14:20:38.9658 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c4af4b1f-92c6-4d27-9427-08dac25d93a3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT101.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6167 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Tegra pre-silicon platforms do not have chip revisions. This makes the revision soc attribute meaningless on these platforms. Instead, populate the revision soc attribute with "platform name + chip revision" for Silicon. For pre-silicon platforms populate it with "platform name" instead. Signed-off-by: Kartik Reviewed-by: Jon Hunter --- v2->v3 * Cosmetic Changes. v1->v2 * Updated commit message. drivers/soc/tegra/fuse/fuse-tegra.c | 22 ++++++++++++++++++++-- drivers/soc/tegra/fuse/tegra-apbmisc.c | 1 + include/soc/tegra/fuse.h | 15 +++++++++++++++ 3 files changed, 36 insertions(+), 2 deletions(-) diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/f= use-tegra.c index ea25a1dcafc2..f02953f793e9 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra.c +++ b/drivers/soc/tegra/fuse/fuse-tegra.c @@ -35,6 +35,19 @@ static const char *tegra_revision_name[TEGRA_REVISION_MA= X] =3D { [TEGRA_REVISION_A04] =3D "A04", }; =20 +static const char *tegra_platform_name[TEGRA_PLATFORM_MAX] =3D { + [TEGRA_PLATFORM_SILICON] =3D "Silicon", + [TEGRA_PLATFORM_QT] =3D "QT", + [TEGRA_PLATFORM_SYSTEM_FPGA] =3D "System FPGA", + [TEGRA_PLATFORM_UNIT_FPGA] =3D "Unit FPGA", + [TEGRA_PLATFORM_ASIM_QT] =3D "Asim QT", + [TEGRA_PLATFORM_ASIM_LINSIM] =3D "Asim Linsim", + [TEGRA_PLATFORM_DSIM_ASIM_LINSIM] =3D "Dsim Asim Linsim", + [TEGRA_PLATFORM_VERIFICATION_SIMULATION] =3D "Verification Simulation", + [TEGRA_PLATFORM_VDK] =3D "VDK", + [TEGRA_PLATFORM_VSP] =3D "VSP", +}; + static const struct of_device_id car_match[] __initconst =3D { { .compatible =3D "nvidia,tegra20-car", }, { .compatible =3D "nvidia,tegra30-car", }, @@ -370,8 +383,13 @@ struct device * __init tegra_soc_device_register(void) return NULL; =20 attr->family =3D kasprintf(GFP_KERNEL, "Tegra"); - attr->revision =3D kasprintf(GFP_KERNEL, "%s", - tegra_revision_name[tegra_sku_info.revision]); + if (tegra_is_silicon()) + attr->revision =3D kasprintf(GFP_KERNEL, "%s %s", + tegra_platform_name[tegra_sku_info.platform], + tegra_revision_name[tegra_sku_info.revision]); + else + attr->revision =3D kasprintf(GFP_KERNEL, "%s", + tegra_platform_name[tegra_sku_info.platform]); attr->soc_id =3D kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id()); attr->custom_attr_group =3D fuse->soc->soc_attr_group; =20 diff --git a/drivers/soc/tegra/fuse/tegra-apbmisc.c b/drivers/soc/tegra/fus= e/tegra-apbmisc.c index 3351bd872ab2..4591c5bcb690 100644 --- a/drivers/soc/tegra/fuse/tegra-apbmisc.c +++ b/drivers/soc/tegra/fuse/tegra-apbmisc.c @@ -156,6 +156,7 @@ void __init tegra_init_revision(void) } =20 tegra_sku_info.sku_id =3D tegra_fuse_read_early(FUSE_SKU_INFO); + tegra_sku_info.platform =3D tegra_get_platform(); } =20 void __init tegra_init_apbmisc(void) diff --git a/include/soc/tegra/fuse.h b/include/soc/tegra/fuse.h index 977c334136e9..a63de5da8124 100644 --- a/include/soc/tegra/fuse.h +++ b/include/soc/tegra/fuse.h @@ -34,6 +34,20 @@ enum tegra_revision { TEGRA_REVISION_MAX, }; =20 +enum tegra_platform { + TEGRA_PLATFORM_SILICON =3D 0, + TEGRA_PLATFORM_QT, + TEGRA_PLATFORM_SYSTEM_FPGA, + TEGRA_PLATFORM_UNIT_FPGA, + TEGRA_PLATFORM_ASIM_QT, + TEGRA_PLATFORM_ASIM_LINSIM, + TEGRA_PLATFORM_DSIM_ASIM_LINSIM, + TEGRA_PLATFORM_VERIFICATION_SIMULATION, + TEGRA_PLATFORM_VDK, + TEGRA_PLATFORM_VSP, + TEGRA_PLATFORM_MAX, +}; + struct tegra_sku_info { int sku_id; int cpu_process_id; @@ -47,6 +61,7 @@ struct tegra_sku_info { int gpu_speedo_id; int gpu_speedo_value; enum tegra_revision revision; + enum tegra_platform platform; }; =20 #ifdef CONFIG_ARCH_TEGRA --=20 2.17.1