From nobody Sat Sep 21 11:52:04 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 956D7C43217 for ; Wed, 19 Oct 2022 10:05:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231297AbiJSKFy (ORCPT ); Wed, 19 Oct 2022 06:05:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42444 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234622AbiJSKFS (ORCPT ); Wed, 19 Oct 2022 06:05:18 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E8041D0C9; Wed, 19 Oct 2022 02:43:52 -0700 (PDT) X-UUID: f32d2bf420ce445486fa0c94b58479ca-20221019 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=Kog1vDR6cA7Cv/+p3jG4ipnaDZd4MDhSuD+VBldspaE=; b=su5nwCGt5Oz+fYz3hMY5xHpH9xtgIqKo0O+NuSgYA2AI9ryoH8ZrwvITVLajtSJt/MpvitTiMTHu9jEakhF74wEV78m8gLDaShdMqkZ7SrXVdlMWxIL5qwm9YKKNsgauPOSnJN7fToz3r1JwwpKl0kwnm5E5QCBwIRRmA5Kyii4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.12,REQID:4709ae2d-bb2f-4f3e-b64f-715b7cc10456,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:62cd327,CLOUDID:16134aa3-73e4-48dd-a911-57b5d5484f14,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: f32d2bf420ce445486fa0c94b58479ca-20221019 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1042997215; Wed, 19 Oct 2022 17:42:21 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 19 Oct 2022 17:42:20 +0800 Received: from mszsdaap41.gcn.mediatek.inc (10.16.6.141) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 19 Oct 2022 17:42:19 +0800 From: To: , , , CC: , , , , , xinlei lee Subject: [PATCH v4] pwm: mtk-disp: Fix the parameters calculated by the enabled flag of disp_pwm Date: Wed, 19 Oct 2022 17:42:18 +0800 Message-ID: <1666172538-11652-1-git-send-email-xinlei.lee@mediatek.com> X-Mailer: git-send-email 2.6.4 MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: xinlei lee In the original mtk_disp_pwm_get_state() function wrongly uses bit 0 of CON0 to judge if the PWM is enabled. However that is indicated by a bit (at a machine dependent position) in the DISP_PWM_EN register. Fix this accordingly. Fixes: 3f2b16734914 ("pwm: mtk-disp: Implement atomic API .get_state()") Signed-off-by: xinlei lee Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Uwe Kleine-K=C3=B6nig --- Rebase on linus/master v6.1-rc1. change since v3: 1. Remove the empty line between Fixes: and S-o-b. change since v2: 1. Modify the code for readability. change since v1: 1. Modify the way to set disp_pwm enbale. --- --- drivers/pwm/pwm-mtk-disp.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-mtk-disp.c b/drivers/pwm/pwm-mtk-disp.c index c605013e4114..3fbb4bae93a4 100644 --- a/drivers/pwm/pwm-mtk-disp.c +++ b/drivers/pwm/pwm-mtk-disp.c @@ -178,7 +178,7 @@ static void mtk_disp_pwm_get_state(struct pwm_chip *chi= p, { struct mtk_disp_pwm *mdp =3D to_mtk_disp_pwm(chip); u64 rate, period, high_width; - u32 clk_div, con0, con1; + u32 clk_div, pwm_en, con0, con1; int err; =20 err =3D clk_prepare_enable(mdp->clk_main); @@ -197,7 +197,8 @@ static void mtk_disp_pwm_get_state(struct pwm_chip *chi= p, rate =3D clk_get_rate(mdp->clk_main); con0 =3D readl(mdp->base + mdp->data->con0); con1 =3D readl(mdp->base + mdp->data->con1); - state->enabled =3D !!(con0 & BIT(0)); + pwm_en =3D readl(mdp->base + DISP_PWM_EN); + state->enabled =3D !!(pwm_en & mdp->data->enable_mask); clk_div =3D FIELD_GET(PWM_CLKDIV_MASK, con0); period =3D FIELD_GET(PWM_PERIOD_MASK, con1); /* --=20 2.18.0