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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT105.mail.protection.outlook.com (10.13.173.164) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5709.10 via Frontend Transport; Mon, 10 Oct 2022 20:28:41 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Mon, 10 Oct 2022 15:28:38 -0500 Subject: [PATCH v6 01/12] x86/cpufeatures: Add Slow Memory Bandwidth Allocation feature flag From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Mon, 10 Oct 2022 15:28:12 -0500 Message-ID: <166543369215.23830.17791885444109680031.stgit@bmoger-ubuntu> In-Reply-To: <166543345606.23830.3120625408601531368.stgit@bmoger-ubuntu> References: <166543345606.23830.3120625408601531368.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2022 20:28:41.3409 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 66fd6e9f-5a64-49fd-95c9-08daaafe0554 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT105.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5337 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the new AMD feature X86_FEATURE_SMBA. With this feature, the QOS enforcement policies can be applied to external slow memory connected to the host. QOS enforcement is accomplished by assigning a Class Of Service (COS) to a processor and specifying allocations or limits for that COS for each resource to be allocated. This feature is identified by the CPUID Function 8000_0020_EBX_x0. CPUID Fn8000_0020_EBX_x0 AMD Bandwidth Enforcement Feature Identifiers (ECX=3D0) Bits Field Name Description 2 L3SBE L3 external slow memory bandwidth enforcement Currently, CXL.memory is the only supported "slow" memory device. With the support of SMBA feature, the hardware enables bandwidth allocation on the slow memory devices. If there are multiple slow memory devices in the system, then the throttling logic groups all the slow sources together and applies the limit on them as a whole. The presence of the SMBA feature(with CXL.memory) is independent of whether slow memory device is actually present in the system. If there is no slow memory in the system, then setting a SMBA limit will have no impact on the performance of the system. Presence of CXL memory can be identified by numactl command. $numactl -H available: 2 nodes (0-1) node 0 cpus: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 node 0 size: 63678 MB node 0 free: 59542 MB node 1 cpus: node 1 size: 16122 MB node 1 free: 15627 MB node distances: node 0 1 0: 10 50 1: 50 10 CPU list for CXL memory will be empty. The cpu-cxl node distance is greater than cpu-to-cpu distances. Node 1 has the CXL memory in this case. CXL memory can also be identified using ACPI SRAT table and memory maps. Feature description is available in the specification, "AMD64 Technology Platform Quality of Service Extensions, Revision: 1.03 Publication # 56375 Revision: 1.03 Issue Date: February 2022". Link: https://www.amd.com/en/support/tech-docs/amd64-technology-platform-qu= ality-service-extensions Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/scattered.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index b71f4f2ecdd5..583b88bcc7e1 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -304,6 +304,7 @@ #define X86_FEATURE_UNRET (11*32+15) /* "" AMD BTB untrain return */ #define X86_FEATURE_USE_IBPB_FW (11*32+16) /* "" Use IBPB during runtime = firmware calls */ #define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM exit w= hen EIBRS is enabled */ +#define X86_FEATURE_SMBA (11*32+18) /* Slow Memory Bandwidth Allocation */ =20 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c index fc01f81f6e2a..5a5f17ed69a2 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -44,6 +44,7 @@ static const struct cpuid_bit cpuid_bits[] =3D { { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 }, { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, + { X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 }, { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, { 0, 0, 0, 0, 0 } From nobody Tue Apr 7 03:32:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6859C433F5 for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT096.mail.protection.outlook.com (10.13.173.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5709.10 via Frontend Transport; Mon, 10 Oct 2022 20:28:47 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Mon, 10 Oct 2022 15:28:45 -0500 Subject: [PATCH v6 02/12] x86/resctrl: Add a new resource type RDT_RESOURCE_SMBA From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Mon, 10 Oct 2022 15:28:44 -0500 Message-ID: <166543372483.23830.14249332360278807042.stgit@bmoger-ubuntu> In-Reply-To: <166543345606.23830.3120625408601531368.stgit@bmoger-ubuntu> References: <166543345606.23830.3120625408601531368.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2022 20:28:47.3543 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 15f1d1e1-2ee7-4dca-4fc1-08daaafe08f1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT096.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6717 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a new resource type RDT_RESOURCE_SMBA to handle the QoS enforcement policies on the external slow memory. Signed-off-by: Babu Moger Reviewed-by: Ingo Molnar --- arch/x86/kernel/cpu/resctrl/core.c | 12 ++++++++++++ arch/x86/kernel/cpu/resctrl/internal.h | 1 + 2 files changed, 13 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index de62b0b87ced..efffce716f3a 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -106,6 +106,18 @@ struct rdt_hw_resource rdt_resources_all[] =3D { .fflags =3D RFTYPE_RES_MB, }, }, + [RDT_RESOURCE_SMBA] =3D + { + .r_resctrl =3D { + .rid =3D RDT_RESOURCE_SMBA, + .name =3D "SMBA", + .cache_level =3D 3, + .domains =3D domain_init(RDT_RESOURCE_SMBA), + .parse_ctrlval =3D parse_bw, + .format_str =3D "%d=3D%*u", + .fflags =3D RFTYPE_RES_MB, + }, + }, }; =20 /* diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 5f7128686cfd..43d9f6f5a931 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -419,6 +419,7 @@ enum resctrl_res_level { RDT_RESOURCE_L3, RDT_RESOURCE_L2, RDT_RESOURCE_MBA, + RDT_RESOURCE_SMBA, =20 /* Must be the last */ RDT_NUM_RESOURCES, From nobody Tue Apr 7 03:32:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 120B6C433F5 for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT024.mail.protection.outlook.com (10.13.172.159) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5709.10 via Frontend Transport; Mon, 10 Oct 2022 20:28:54 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Mon, 10 Oct 2022 15:28:52 -0500 Subject: [PATCH v6 03/12] x86/cpufeatures: Add Bandwidth Monitoring Event Configuration feature flag From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Mon, 10 Oct 2022 15:28:52 -0500 Message-ID: <166543373210.23830.13288254739033595117.stgit@bmoger-ubuntu> In-Reply-To: <166543345606.23830.3120625408601531368.stgit@bmoger-ubuntu> References: <166543345606.23830.3120625408601531368.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2022 20:28:54.7056 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 079137d6-572e-45af-dfca-08daaafe0d4b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT024.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4237 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Newer AMD processors support the new feature Bandwidth Monitoring Event Configuration (BMEC). The feature support is identified via CPUID Fn8000_0020_EBX_x0 (ECX=3D0). Bits Field Name Description 3 EVT_CFG Bandwidth Monitoring Event Configuration (BMEC) Currently, the bandwidth monitoring events mbm_total_bytes and mbm_local_bytes are set to count all the total and local reads/writes respectively. With the introduction of slow memory, the two counters are not enough to count all the different types of memory events. With the feature BMEC, the users have the option to configure mbm_total_bytes and mbm_local_bytes to count the specific type of events. Each BMEC event has a configuration MSR, QOS_EVT_CFG (0xc000_0400h + EventID) which contains one field for each bandwidth type that can be used to configure the bandwidth event to track any combination of supported bandwidth types. The event will count requests from every bandwidth type bit that is set in the corresponding configuration register. Following are the types of events supported: =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Bits Description =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D 6 Dirty Victims from the QOS domain to all types of memory 5 Reads to slow memory in the non-local NUMA domain 4 Reads to slow memory in the local NUMA domain 3 Non-temporal writes to non-local NUMA domain 2 Non-temporal writes to local NUMA domain 1 Reads to memory in the non-local NUMA domain 0 Reads to memory in the local NUMA domain =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D By default, the mbm_total_bytes configuration is set to 0x7F to count all the event types and the mbm_local_bytes configuration is set to 0x15 to count all the local memory events. Feature description is available in the specification, "AMD64 Technology Platform Quality of Service Extensions, Revision: 1.03 Publication Link: https://www.amd.com/en/support/tech-docs/amd64-technology-platform-qu= ality-service-extensions Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/cpuid-deps.c | 1 + arch/x86/kernel/cpu/scattered.c | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 583b88bcc7e1..bf0fd022e80a 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -305,6 +305,7 @@ #define X86_FEATURE_USE_IBPB_FW (11*32+16) /* "" Use IBPB during runtime = firmware calls */ #define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM exit w= hen EIBRS is enabled */ #define X86_FEATURE_SMBA (11*32+18) /* Slow Memory Bandwidth Allocation */ +#define X86_FEATURE_BMEC (11*32+19) /* AMD Bandwidth Monitoring Event Con= figuration (BMEC) */ =20 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-d= eps.c index c881bcafba7d..4555f9596ccf 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -68,6 +68,7 @@ static const struct cpuid_dep cpuid_deps[] =3D { { X86_FEATURE_CQM_OCCUP_LLC, X86_FEATURE_CQM_LLC }, { X86_FEATURE_CQM_MBM_TOTAL, X86_FEATURE_CQM_LLC }, { X86_FEATURE_CQM_MBM_LOCAL, X86_FEATURE_CQM_LLC }, + { X86_FEATURE_BMEC, X86_FEATURE_CQM_LLC }, { X86_FEATURE_AVX512_BF16, X86_FEATURE_AVX512VL }, { X86_FEATURE_AVX512_FP16, X86_FEATURE_AVX512BW }, { X86_FEATURE_ENQCMD, X86_FEATURE_XSAVES }, diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c index 5a5f17ed69a2..67c4d24e06ef 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -45,6 +45,7 @@ static const struct cpuid_bit cpuid_bits[] =3D { { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, { X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 }, + { X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 }, { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, { 0, 0, 0, 0, 0 } From nobody Tue Apr 7 03:32:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6656CC43217 for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT020.mail.protection.outlook.com (10.13.172.224) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5709.10 via Frontend Transport; Mon, 10 Oct 2022 20:29:14 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Mon, 10 Oct 2022 15:29:12 -0500 Subject: [PATCH v6 04/12] x86/resctrl: Include new features in command line options From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Mon, 10 Oct 2022 15:28:59 -0500 Message-ID: <166543373926.23830.6551235898170426788.stgit@bmoger-ubuntu> In-Reply-To: <166543345606.23830.3120625408601531368.stgit@bmoger-ubuntu> References: <166543345606.23830.3120625408601531368.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2022 20:29:14.8753 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1f30bd3b-9fda-46c8-86ac-08daaafe1951 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT020.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7609 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the command line options to disable the new features. smba : Slow Memory Bandwidth Allocation bmec : Bandwidth Monitor Event Configuration. Signed-off-by: Babu Moger --- Documentation/admin-guide/kernel-parameters.txt | 2 +- arch/x86/kernel/cpu/resctrl/core.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index 2bc11a61c4d0..d616366e964a 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -5173,7 +5173,7 @@ rdt=3D [HW,X86,RDT] Turn on/off individual RDT features. List is: cmt, mbmtotal, mbmlocal, l3cat, l3cdp, l2cat, l2cdp, - mba. + mba, smba, bmec. E.g. to turn on cmt and turn off mba use: rdt=3Dcmt,!mba =20 diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index efffce716f3a..c7561c613209 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -665,6 +665,8 @@ enum { RDT_FLAG_L2_CAT, RDT_FLAG_L2_CDP, RDT_FLAG_MBA, + RDT_FLAG_SMBA, + RDT_FLAG_BMEC, }; =20 #define RDT_OPT(idx, n, f) \ @@ -688,6 +690,8 @@ static struct rdt_options rdt_options[] __initdata =3D= { RDT_OPT(RDT_FLAG_L2_CAT, "l2cat", X86_FEATURE_CAT_L2), RDT_OPT(RDT_FLAG_L2_CDP, "l2cdp", X86_FEATURE_CDP_L2), RDT_OPT(RDT_FLAG_MBA, "mba", X86_FEATURE_MBA), + RDT_OPT(RDT_FLAG_SMBA, "smba", X86_FEATURE_SMBA), + RDT_OPT(RDT_FLAG_BMEC, "bmec", X86_FEATURE_BMEC), }; #define NUM_RDT_OPTIONS ARRAY_SIZE(rdt_options) =20 From nobody Tue Apr 7 03:32:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80723C433F5 for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT039.mail.protection.outlook.com (10.13.172.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5709.10 via Frontend Transport; Mon, 10 Oct 2022 20:29:21 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Mon, 10 Oct 2022 15:29:19 -0500 Subject: [PATCH v6 05/12] x86/resctrl: Detect and configure Slow Memory Bandwidth allocation From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Mon, 10 Oct 2022 15:29:19 -0500 Message-ID: <166543375907.23830.9540051258372039106.stgit@bmoger-ubuntu> In-Reply-To: <166543345606.23830.3120625408601531368.stgit@bmoger-ubuntu> References: <166543345606.23830.3120625408601531368.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2022 20:29:21.6703 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b81e9dd2-e92c-4f52-5a9c-08daaafe1d5e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT039.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6764 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The QoS slow memory configuration details are available via CPUID_Fn80000020_EDX_x02. Detect the available details and initialize the rest to defaults. Signed-off-by: Babu Moger --- arch/x86/kernel/cpu/resctrl/core.c | 29 +++++++++++++++++++++++++= ++-- arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 2 +- arch/x86/kernel/cpu/resctrl/internal.h | 1 + arch/x86/kernel/cpu/resctrl/rdtgroup.c | 16 ++++++++++------ 4 files changed, 39 insertions(+), 9 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index c7561c613209..d79f494a4e91 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -231,9 +231,15 @@ static bool __rdt_get_mem_config_amd(struct rdt_resour= ce *r) struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r); union cpuid_0x10_3_eax eax; union cpuid_0x10_x_edx edx; - u32 ebx, ecx; + u32 ebx, ecx, subleaf; + + /* + * Query CPUID_Fn80000020_EDX_x01 for MBA and + * CPUID_Fn80000020_EDX_x02 for SMBA + */ + subleaf =3D (r->rid =3D=3D RDT_RESOURCE_SMBA) ? 2 : 1; =20 - cpuid_count(0x80000020, 1, &eax.full, &ebx, &ecx, &edx.full); + cpuid_count(0x80000020, subleaf, &eax.full, &ebx, &ecx, &edx.full); hw_res->num_closid =3D edx.split.cos_max + 1; r->default_ctrl =3D MAX_MBA_BW_AMD; =20 @@ -756,6 +762,19 @@ static __init bool get_mem_config(void) return false; } =20 +static __init bool get_slow_mem_config(void) +{ + struct rdt_hw_resource *hw_res =3D &rdt_resources_all[RDT_RESOURCE_SMBA]; + + if (!rdt_cpu_has(X86_FEATURE_SMBA)) + return false; + + if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD) + return __rdt_get_mem_config_amd(&hw_res->r_resctrl); + + return false; +} + static __init bool get_rdt_alloc_resources(void) { struct rdt_resource *r; @@ -786,6 +805,9 @@ static __init bool get_rdt_alloc_resources(void) if (get_mem_config()) ret =3D true; =20 + if (get_slow_mem_config()) + ret =3D true; + return ret; } =20 @@ -875,6 +897,9 @@ static __init void rdt_init_res_defs_amd(void) } else if (r->rid =3D=3D RDT_RESOURCE_MBA) { hw_res->msr_base =3D MSR_IA32_MBA_BW_BASE; hw_res->msr_update =3D mba_wrmsr_amd; + } else if (r->rid =3D=3D RDT_RESOURCE_SMBA) { + hw_res->msr_base =3D MSR_IA32_SMBA_BW_BASE; + hw_res->msr_update =3D mba_wrmsr_amd; } } } diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cp= u/resctrl/ctrlmondata.c index 1dafbdc5ac31..42e2ef6fbdb8 100644 --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c @@ -210,7 +210,7 @@ static int parse_line(char *line, struct resctrl_schema= *s, unsigned long dom_id; =20 if (rdtgrp->mode =3D=3D RDT_MODE_PSEUDO_LOCKSETUP && - r->rid =3D=3D RDT_RESOURCE_MBA) { + (r->rid =3D=3D RDT_RESOURCE_MBA || r->rid =3D=3D RDT_RESOURCE_SMBA)) { rdt_last_cmd_puts("Cannot pseudo-lock MBA resource\n"); return -EINVAL; } diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 43d9f6f5a931..16e3c6e03c79 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -14,6 +14,7 @@ #define MSR_IA32_L2_CBM_BASE 0xd10 #define MSR_IA32_MBA_THRTL_BASE 0xd50 #define MSR_IA32_MBA_BW_BASE 0xc0000200 +#define MSR_IA32_SMBA_BW_BASE 0xc0000280 =20 #define MSR_IA32_QM_CTR 0x0c8e #define MSR_IA32_QM_EVTSEL 0x0c8d diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index e5a48f05e787..1271fd1ae2f3 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1213,7 +1213,7 @@ static bool rdtgroup_mode_test_exclusive(struct rdtgr= oup *rdtgrp) =20 list_for_each_entry(s, &resctrl_schema_all, list) { r =3D s->res; - if (r->rid =3D=3D RDT_RESOURCE_MBA) + if (r->rid =3D=3D RDT_RESOURCE_MBA || r->rid =3D=3D RDT_RESOURCE_SMBA) continue; has_cache =3D true; list_for_each_entry(d, &r->domains, list) { @@ -1402,7 +1402,8 @@ static int rdtgroup_size_show(struct kernfs_open_file= *of, ctrl =3D resctrl_arch_get_config(r, d, closid, type); - if (r->rid =3D=3D RDT_RESOURCE_MBA) + if (r->rid =3D=3D RDT_RESOURCE_MBA || + r->rid =3D=3D RDT_RESOURCE_SMBA) size =3D ctrl; else size =3D rdtgroup_cbm_to_size(r, d, ctrl); @@ -2845,7 +2846,8 @@ static int rdtgroup_init_alloc(struct rdtgroup *rdtgr= p) =20 list_for_each_entry(s, &resctrl_schema_all, list) { r =3D s->res; - if (r->rid =3D=3D RDT_RESOURCE_MBA) { + if (r->rid =3D=3D RDT_RESOURCE_MBA || + r->rid =3D=3D RDT_RESOURCE_SMBA) { rdtgroup_init_mba(r, rdtgrp->closid); if (is_mba_sc(r)) continue; @@ -3287,7 +3289,8 @@ void resctrl_offline_domain(struct rdt_resource *r, s= truct rdt_domain *d) { lockdep_assert_held(&rdtgroup_mutex); =20 - if (supports_mba_mbps() && r->rid =3D=3D RDT_RESOURCE_MBA) + if (supports_mba_mbps() && + (r->rid =3D=3D RDT_RESOURCE_MBA || r->rid =3D=3D RDT_RESOURCE_SMBA)) mba_sc_domain_destroy(r, d); =20 if (!r->mon_capable) @@ -3354,8 +3357,9 @@ int resctrl_online_domain(struct rdt_resource *r, str= uct rdt_domain *d) =20 lockdep_assert_held(&rdtgroup_mutex); =20 - if (supports_mba_mbps() && r->rid =3D=3D RDT_RESOURCE_MBA) - /* RDT_RESOURCE_MBA is never mon_capable */ + if (supports_mba_mbps() && + (r->rid =3D=3D RDT_RESOURCE_MBA || r->rid =3D=3D RDT_RESOURCE_MBA)) + /* RDT_RESOURCE_MBA (or SMBA) is never mon_capable */ return mba_sc_domain_allocate(r, d); =20 if (!r->mon_capable) From nobody Tue Apr 7 03:32:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B77E5C433F5 for ; Mon, 10 Oct 2022 20:31:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230209AbiJJUbD (ORCPT ); Mon, 10 Oct 2022 16:31:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57484 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230089AbiJJUaE (ORCPT ); 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Mon, 10 Oct 2022 15:29:26 -0500 Subject: [PATCH v6 06/12] x86/resctrl: Introduce data structure to support monitor configuration From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Mon, 10 Oct 2022 15:29:26 -0500 Message-ID: <166543376626.23830.5138502593585732085.stgit@bmoger-ubuntu> In-Reply-To: <166543345606.23830.3120625408601531368.stgit@bmoger-ubuntu> References: <166543345606.23830.3120625408601531368.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT046:EE_|DS0PR12MB6629:EE_ X-MS-Office365-Filtering-Correlation-Id: 52442821-4cd1-4b45-83d4-08daaafe21b5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2022 20:29:28.9524 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 52442821-4cd1-4b45-83d4-08daaafe21b5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT046.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6629 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a new field in mon_evt to support Bandwidth Monitoring Event Configuration(BMEC) and also update the "mon_features" display. The sysfs file "mon_features" will display the monitor configuration if supported. Before the change. $cat /sys/fs/resctrl/info/L3_MON/mon_features llc_occupancy mbm_total_bytes mbm_local_bytes After the change if BMEC is supported. $cat /sys/fs/resctrl/info/L3_MON/mon_features llc_occupancy mbm_total_bytes mbm_total_config mbm_local_bytes mbm_local_config Signed-off-by: Babu Moger --- arch/x86/kernel/cpu/resctrl/core.c | 3 ++- arch/x86/kernel/cpu/resctrl/internal.h | 4 +++- arch/x86/kernel/cpu/resctrl/monitor.c | 7 ++++++- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 5 ++++- 4 files changed, 15 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index d79f494a4e91..46813b1c50c2 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -814,6 +814,7 @@ static __init bool get_rdt_alloc_resources(void) static __init bool get_rdt_mon_resources(void) { struct rdt_resource *r =3D &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl; + bool mon_configurable =3D rdt_cpu_has(X86_FEATURE_BMEC); =20 if (rdt_cpu_has(X86_FEATURE_CQM_OCCUP_LLC)) rdt_mon_features |=3D (1 << QOS_L3_OCCUP_EVENT_ID); @@ -825,7 +826,7 @@ static __init bool get_rdt_mon_resources(void) if (!rdt_mon_features) return false; =20 - return !rdt_get_mon_l3_config(r); + return !rdt_get_mon_l3_config(r, mon_configurable); } =20 static __init void __check_quirks_intel(void) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 16e3c6e03c79..b458f768f30c 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -63,11 +63,13 @@ DECLARE_STATIC_KEY_FALSE(rdt_mon_enable_key); * struct mon_evt - Entry in the event list of a resource * @evtid: event id * @name: name of the event + * @configurable: true if the event is configurable * @list: entry in &rdt_resource->evt_list */ struct mon_evt { enum resctrl_event_id evtid; char *name; + bool configurable; struct list_head list; }; =20 @@ -522,7 +524,7 @@ int closids_supported(void); void closid_free(int closid); int alloc_rmid(void); void free_rmid(u32 rmid); -int rdt_get_mon_l3_config(struct rdt_resource *r); +int rdt_get_mon_l3_config(struct rdt_resource *r, bool configurable); void mon_event_count(void *info); int rdtgroup_mondata_show(struct seq_file *m, void *arg); void mon_event_read(struct rmid_read *rr, struct rdt_resource *r, diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index efe0c30d3a12..4b8adb7f1c5c 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -746,7 +746,7 @@ static void l3_mon_evt_init(struct rdt_resource *r) list_add_tail(&mbm_local_event.list, &r->evt_list); } =20 -int rdt_get_mon_l3_config(struct rdt_resource *r) +int rdt_get_mon_l3_config(struct rdt_resource *r, bool configurable) { unsigned int mbm_offset =3D boot_cpu_data.x86_cache_mbm_width_offset; struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r); @@ -783,6 +783,11 @@ int rdt_get_mon_l3_config(struct rdt_resource *r) if (ret) return ret; =20 + if (configurable) { + mbm_total_event.configurable =3D true; + mbm_local_event.configurable =3D true; + } + l3_mon_evt_init(r); =20 r->mon_capable =3D true; diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 1271fd1ae2f3..5f0ef1bf4c78 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1001,8 +1001,11 @@ static int rdt_mon_features_show(struct kernfs_open_= file *of, struct rdt_resource *r =3D of->kn->parent->priv; struct mon_evt *mevt; =20 - list_for_each_entry(mevt, &r->evt_list, list) + list_for_each_entry(mevt, &r->evt_list, list) { seq_printf(seq, "%s\n", mevt->name); + if (mevt->configurable) + seq_printf(seq, "%s_config\n", mevt->name); + } =20 return 0; } From nobody Tue Apr 7 03:32:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13C67C433FE for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT009.mail.protection.outlook.com (10.13.173.20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5709.10 via Frontend Transport; Mon, 10 Oct 2022 20:29:36 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Mon, 10 Oct 2022 15:29:34 -0500 Subject: [PATCH v6 07/12] x86/resctrl: Add sysfs interface to read mbm_total_bytes event configuration From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Mon, 10 Oct 2022 15:29:33 -0500 Message-ID: <166543377343.23830.10906905028303177147.stgit@bmoger-ubuntu> In-Reply-To: <166543345606.23830.3120625408601531368.stgit@bmoger-ubuntu> References: <166543345606.23830.3120625408601531368.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2022 20:29:36.0182 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0e49a088-e825-4021-4992-08daaafe25e9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT009.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6970 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The current event configuration can be viewed by the user by reading the configuration file /sys/fs/resctrl/info/L3_MON/mbm_total_config. Following are the types of events supported: =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Bits Description =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D 6 Dirty Victims from the QOS domain to all types of memory 5 Reads to slow memory in the non-local NUMA domain 4 Reads to slow memory in the local NUMA domain 3 Non-temporal writes to non-local NUMA domain 2 Non-temporal writes to local NUMA domain 1 Reads to memory in the non-local NUMA domain 0 Reads to memory in the local NUMA domain =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D By default, the mbm_total_bytes configuration is set to 0x7f to count all the event types. The event configuration settings are domain specific. Changing the configuration on one CPU in a domain would affect the whole domain. For example: $cat /sys/fs/resctrl/info/L3_MON/mbm_total_config 0=3D0x7f;1=3D0x7f;2=3D0x7f;3=3D0x7f In this case, the event mbm_total_bytes is currently configured with 0x7f on domains 0 to 3. Signed-off-by: Babu Moger --- arch/x86/kernel/cpu/resctrl/core.c | 3 + arch/x86/kernel/cpu/resctrl/internal.h | 2 + arch/x86/kernel/cpu/resctrl/rdtgroup.c | 76 ++++++++++++++++++++++++++++= ++++ 3 files changed, 81 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 46813b1c50c2..758c5d7553a4 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -826,6 +826,9 @@ static __init bool get_rdt_mon_resources(void) if (!rdt_mon_features) return false; =20 + if (mon_configurable) + mbm_config_rftype_init(); + return !rdt_get_mon_l3_config(r, mon_configurable); } =20 diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index b458f768f30c..326a1b582f38 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -15,6 +15,7 @@ #define MSR_IA32_MBA_THRTL_BASE 0xd50 #define MSR_IA32_MBA_BW_BASE 0xc0000200 #define MSR_IA32_SMBA_BW_BASE 0xc0000280 +#define MSR_IA32_EVT_CFG_BASE 0xc0000400 =20 #define MSR_IA32_QM_CTR 0x0c8e #define MSR_IA32_QM_EVTSEL 0x0c8d @@ -541,5 +542,6 @@ bool has_busy_rmid(struct rdt_resource *r, struct rdt_d= omain *d); void __check_limbo(struct rdt_domain *d, bool force_free); void rdt_domain_reconfigure_cdp(struct rdt_resource *r); void __init thread_throttle_mode_init(void); +void __init mbm_config_rftype_init(void); =20 #endif /* _ASM_X86_RESCTRL_INTERNAL_H */ diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 5f0ef1bf4c78..0982845594d0 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1423,6 +1423,67 @@ static int rdtgroup_size_show(struct kernfs_open_fil= e *of, return ret; } =20 +struct mon_config_info { + u32 evtid; + u32 mon_config; +}; + +static void mon_event_config_read(void *info) +{ + struct mon_config_info *mon_info =3D info; + u32 h, msr_index; + + switch (mon_info->evtid) { + case QOS_L3_MBM_TOTAL_EVENT_ID: + msr_index =3D 0; + break; + case QOS_L3_MBM_LOCAL_EVENT_ID: + msr_index =3D 1; + break; + default: + /* Not expected to come here */ + return; + } + + rdmsr(MSR_IA32_EVT_CFG_BASE + msr_index, mon_info->mon_config, h); +} + +static void mondata_config_read(struct rdt_domain *d, struct mon_config_in= fo *mon_info) +{ + smp_call_function_any(&d->cpu_mask, mon_event_config_read, mon_info, 1); +} + +static int mbm_config_show(struct seq_file *s, struct rdt_resource *r, u32= evtid) +{ + struct mon_config_info mon_info =3D {0}; + struct rdt_domain *dom; + bool sep =3D false; + + list_for_each_entry(dom, &r->domains, list) { + if (sep) + seq_puts(s, ";"); + + mon_info.evtid =3D evtid; + mondata_config_read(dom, &mon_info); + + seq_printf(s, "%d=3D0x%02x", dom->id, mon_info.mon_config); + sep =3D true; + } + seq_puts(s, "\n"); + + return 0; +} + +static int mbm_total_config_show(struct kernfs_open_file *of, + struct seq_file *seq, void *v) +{ + struct rdt_resource *r =3D of->kn->parent->priv; + + mbm_config_show(seq, r, QOS_L3_MBM_TOTAL_EVENT_ID); + + return 0; +} + /* rdtgroup information files for one cache resource. */ static struct rftype res_common_files[] =3D { { @@ -1521,6 +1582,12 @@ static struct rftype res_common_files[] =3D { .seq_show =3D max_threshold_occ_show, .fflags =3D RF_MON_INFO | RFTYPE_RES_CACHE, }, + { + .name =3D "mbm_total_config", + .mode =3D 0644, + .kf_ops =3D &rdtgroup_kf_single_ops, + .seq_show =3D mbm_total_config_show, + }, { .name =3D "cpus", .mode =3D 0644, @@ -1627,6 +1694,15 @@ void __init thread_throttle_mode_init(void) rft->fflags =3D RF_CTRL_INFO | RFTYPE_RES_MB; } =20 +void __init mbm_config_rftype_init(void) +{ + struct rftype *rft; + + rft =3D rdtgroup_get_rftype_by_name("mbm_total_config"); + if (rft) + rft->fflags =3D RF_MON_INFO | RFTYPE_RES_CACHE; +} + /** * rdtgroup_kn_mode_restrict - Restrict user access to named resctrl file * @r: The resource group with which the file is associated. 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT069.mail.protection.outlook.com (10.13.173.202) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5709.10 via Frontend Transport; Mon, 10 Oct 2022 20:29:53 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Mon, 10 Oct 2022 15:29:51 -0500 Subject: [PATCH v6 08/12] x86/resctrl: Add sysfs interface to read mbm_local_bytes event configuration From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Mon, 10 Oct 2022 15:29:40 -0500 Message-ID: <166543378060.23830.6262795783125938383.stgit@bmoger-ubuntu> In-Reply-To: <166543345606.23830.3120625408601531368.stgit@bmoger-ubuntu> References: <166543345606.23830.3120625408601531368.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2022 20:29:53.6468 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f596394e-8c08-436b-96d6-08daaafe306d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT069.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5949 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The current event configuration can be viewed by the user by reading the configuration file /sys/fs/resctrl/info/L3_MON/mbm_local_config. Following are the types of events supported: =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Bits Description =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D 6 Dirty Victims from the QOS domain to all types of memory 5 Reads to slow memory in the non-local NUMA domain 4 Reads to slow memory in the local NUMA domain 3 Non-temporal writes to non-local NUMA domain 2 Non-temporal writes to local NUMA domain 1 Reads to memory in the non-local NUMA domain 0 Reads to memory in the local NUMA domain =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D By default, the mbm_local_bytes configuration is set to 0x15 to count all the local event types. The event configuration settings are domain specific. Changing the configuration on one CPU in a domain would affect the whole domain. For example: $cat /sys/fs/resctrl/info/L3_MON/mbm_local_config 0=3D0x15;1=3D0x15;2=3D0x15;3=3D0x15 In this case the event mbm_local_bytes is currently configured with 0x15 on domains 0 to 3. Signed-off-by: Babu Moger --- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 0982845594d0..305fb0475970 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1484,6 +1484,16 @@ static int mbm_total_config_show(struct kernfs_open_= file *of, return 0; } =20 +static int mbm_local_config_show(struct kernfs_open_file *of, + struct seq_file *seq, void *v) +{ + struct rdt_resource *r =3D of->kn->parent->priv; + + mbm_config_show(seq, r, QOS_L3_MBM_LOCAL_EVENT_ID); + + return 0; +} + /* rdtgroup information files for one cache resource. */ static struct rftype res_common_files[] =3D { { @@ -1588,6 +1598,12 @@ static struct rftype res_common_files[] =3D { .kf_ops =3D &rdtgroup_kf_single_ops, .seq_show =3D mbm_total_config_show, }, + { + .name =3D "mbm_local_config", + .mode =3D 0644, + .kf_ops =3D &rdtgroup_kf_single_ops, + .seq_show =3D mbm_local_config_show, + }, { .name =3D "cpus", .mode =3D 0644, @@ -1701,6 +1717,10 @@ void __init mbm_config_rftype_init(void) rft =3D rdtgroup_get_rftype_by_name("mbm_total_config"); if (rft) rft->fflags =3D RF_MON_INFO | RFTYPE_RES_CACHE; + + rft =3D rdtgroup_get_rftype_by_name("mbm_local_config"); + if (rft) + rft->fflags =3D RF_MON_INFO | RFTYPE_RES_CACHE; } =20 /** From nobody Tue Apr 7 03:32:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E57FC433F5 for ; Mon, 10 Oct 2022 20:31:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230261AbiJJUbc (ORCPT ); Mon, 10 Oct 2022 16:31:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33170 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229817AbiJJUak (ORCPT ); Mon, 10 Oct 2022 16:30:40 -0400 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2040.outbound.protection.outlook.com [40.107.93.40]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E1DA27FDC; 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Mon, 10 Oct 2022 20:30:05 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT099.mail.protection.outlook.com (10.13.172.241) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5709.10 via Frontend Transport; Mon, 10 Oct 2022 20:30:05 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Mon, 10 Oct 2022 15:30:03 -0500 Subject: [PATCH v6 09/12] x86/resctrl: Add sysfs interface to write mbm_total_bytes event configuration From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Mon, 10 Oct 2022 15:29:58 -0500 Message-ID: <166543379820.23830.9029078361756200962.stgit@bmoger-ubuntu> In-Reply-To: <166543345606.23830.3120625408601531368.stgit@bmoger-ubuntu> References: <166543345606.23830.3120625408601531368.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2022 20:30:05.8277 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ab4de28d-7c94-40b4-3e2b-08daaafe37b0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT099.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6725 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The current event configuration can be changed by the user by writing to the configuration file /sys/fs/resctrl/info/L3_MON/mbm_total_config. The event configuration settings are domain specific and will affect all the CPUs in the domain. Following are the types of events supported: =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Bits Description =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D 6 Dirty Victims from the QOS domain to all types of memory 5 Reads to slow memory in the non-local NUMA domain 4 Reads to slow memory in the local NUMA domain 3 Non-temporal writes to non-local NUMA domain 2 Non-temporal writes to local NUMA domain 1 Reads to memory in the non-local NUMA domain 0 Reads to memory in the local NUMA domain =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D For example: To change the mbm_total_bytes to count only reads on domain 0. To achieve this, the bits 0, 1, 4 and 5 needs to be set which is 110011b (in hex 0x33). Run the command. $echo 0=3D0x33 > /sys/fs/resctrl/info/L3_MON/mbm_total_config To change the mbm_total_bytes to count all the slow memory reads on domain 1. To achieve this, the bits 4 and 5 needs to be set which is 110000b (in hex 0x30). Run the command. $echo 1=3D0x30 > /sys/fs/resctrl/info/L3_MON/mbm_total_config Signed-off-by: Babu Moger --- arch/x86/kernel/cpu/resctrl/internal.h | 23 +++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 146 ++++++++++++++++++++++++++++= ++++ 2 files changed, 169 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 326a1b582f38..c42b12934a0e 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -42,6 +42,29 @@ */ #define MBM_CNTR_WIDTH_OFFSET_MAX (62 - MBM_CNTR_WIDTH_BASE) =20 +/* Reads to Local DRAM Memory */ +#define READS_TO_LOCAL_MEM BIT(0) + +/* Reads to Remote DRAM Memory */ +#define READS_TO_REMOTE_MEM BIT(1) + +/* Non-Temporal Writes to Local Memory */ +#define NON_TEMP_WRITE_TO_LOCAL_MEM BIT(2) + +/* Non-Temporal Writes to Remote Memory */ +#define NON_TEMP_WRITE_TO_REMOTE_MEM BIT(3) + +/* Reads to Local Memory the system identifies as "Slow Memory" */ +#define READS_TO_LOCAL_S_MEM BIT(4) + +/* Reads to Remote Memory the system identifies as "Slow Memory" */ +#define READS_TO_REMOTE_S_MEM BIT(5) + +/* Dirty Victims to All Types of Memory */ +#define DIRTY_VICTIMS_TO_ALL_MEM BIT(6) + +/* Max event bits supported */ +#define MAX_EVT_CONFIG_BITS GENMASK(6, 0) =20 struct rdt_fs_context { struct kernfs_fs_context kfc; diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 305fb0475970..25ff56ecb817 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1494,6 +1494,151 @@ static int mbm_local_config_show(struct kernfs_open= _file *of, return 0; } =20 +static void mon_event_config_write(void *info) +{ + struct mon_config_info *mon_info =3D info; + u32 msr_index; + + switch (mon_info->evtid) { + case QOS_L3_MBM_TOTAL_EVENT_ID: + msr_index =3D 0; + break; + case QOS_L3_MBM_LOCAL_EVENT_ID: + msr_index =3D 1; + break; + default: + /* Not expected to come here */ + return; + } + + wrmsr(MSR_IA32_EVT_CFG_BASE + msr_index, mon_info->mon_config, 0); +} + +static int mbm_config_write(struct rdt_resource *r, struct rdt_domain *d, + u32 evtid, u32 val) +{ + struct mon_config_info mon_info =3D {0}; + cpumask_var_t cpu_mask; + int ret =3D 0, cpu; + + rdt_last_cmd_clear(); + + /* mon_config cannot be more than the supported set of events */ + if (val > MAX_EVT_CONFIG_BITS) { + rdt_last_cmd_puts("Invalid event configuration\n"); + return -EINVAL; + } + + cpus_read_lock(); + + if (!zalloc_cpumask_var(&cpu_mask, GFP_KERNEL)) { + rdt_last_cmd_puts("cpu_mask allocation failed\n"); + ret =3D -ENOMEM; + goto e_unlock; + } + + /* + * Read the current config value first. If both are same then + * we dont need to write it again. + */ + mon_info.evtid =3D evtid; + mondata_config_read(d, &mon_info); + if (mon_info.mon_config =3D=3D val) + goto e_cpumask; + + mon_info.mon_config =3D val; + + /* Pick all the CPUs in the domain instance */ + for_each_cpu(cpu, &d->cpu_mask) + cpumask_set_cpu(cpu, cpu_mask); + + /* + * Update MSR_IA32_EVT_CFG_BASE MSRs on all the CPUs in + * cpu_mask. The MSRs offset from MSR MSR_IA32_EVT_CFG_BASE + * are scoped at the domain level. Writing any of these MSRs + * on one CPU is supposed to be observed by all CPUs in the + * domain. However, the hardware team recommends to update + * these MSRs on all the CPUs in the domain. + */ + on_each_cpu_mask(cpu_mask, mon_event_config_write, &mon_info, 1); + + /* + * When an Event Configuration is changed, the bandwidth counters + * for all RMIDs and Events will be cleared by the hardware. The + * hardware also sets MSR_IA32_QM_CTR.Unavailable (bit 62) for + * every RMID on the next read to any event for every RMID. + * Subsequent reads will have MSR_IA32_QM_CTR.Unavailable (bit 62) + * cleared while it is tracked by the hardware. Clear the + * mbm_local and mbm_total counts for all the RMIDs. + */ + memset(d->mbm_local, 0, sizeof(struct mbm_state) * r->num_rmid); + memset(d->mbm_total, 0, sizeof(struct mbm_state) * r->num_rmid); + +e_cpumask: + free_cpumask_var(cpu_mask); + +e_unlock: + cpus_read_unlock(); + + return ret; +} + +static int mon_config_parse(struct rdt_resource *r, char *tok, u32 evtid) +{ + char *dom_str =3D NULL, *id_str; + struct rdt_domain *d; + unsigned long dom_id, val; + int ret =3D 0; + +next: + if (!tok || tok[0] =3D=3D '\0') + return 0; + + /* Start processing the strings for each domain */ + dom_str =3D strim(strsep(&tok, ";")); + id_str =3D strsep(&dom_str, "=3D"); + + if (!dom_str || kstrtoul(id_str, 10, &dom_id)) { + rdt_last_cmd_puts("Missing '=3D' or non-numeric domain id\n"); + return -EINVAL; + } + + if (!dom_str || kstrtoul(dom_str, 16, &val)) { + rdt_last_cmd_puts("Missing '=3D' or non-numeric event configuration valu= e\n"); + return -EINVAL; + } + + list_for_each_entry(d, &r->domains, list) { + if (d->id =3D=3D dom_id) { + ret =3D mbm_config_write(r, d, evtid, val); + if (ret) + return -EINVAL; + goto next; + } + } + + return -EINVAL; +} + +static ssize_t mbm_total_config_write(struct kernfs_open_file *of, + char *buf, size_t nbytes, loff_t off) +{ + struct rdt_resource *r =3D of->kn->parent->priv; + int ret; + + /* Valid input requires a trailing newline */ + if (nbytes =3D=3D 0 || buf[nbytes - 1] !=3D '\n') + return -EINVAL; + + rdt_last_cmd_clear(); + + buf[nbytes - 1] =3D '\0'; + + ret =3D mon_config_parse(r, buf, QOS_L3_MBM_TOTAL_EVENT_ID); + + return ret ?: nbytes; +} + /* rdtgroup information files for one cache resource. */ static struct rftype res_common_files[] =3D { { @@ -1597,6 +1742,7 @@ static struct rftype res_common_files[] =3D { .mode =3D 0644, .kf_ops =3D &rdtgroup_kf_single_ops, .seq_show =3D mbm_total_config_show, + .write =3D mbm_total_config_write, }, { .name =3D "mbm_local_config", From nobody Tue Apr 7 03:32:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FDC4C4332F for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT046.mail.protection.outlook.com (10.13.172.121) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5709.10 via Frontend Transport; Mon, 10 Oct 2022 20:30:28 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Mon, 10 Oct 2022 15:30:26 -0500 Subject: [PATCH v6 10/12] x86/resctrl: Add sysfs interface to write mbm_local_bytes event configuration From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Mon, 10 Oct 2022 15:30:10 -0500 Message-ID: <166543381031.23830.5870006320102530890.stgit@bmoger-ubuntu> In-Reply-To: <166543345606.23830.3120625408601531368.stgit@bmoger-ubuntu> References: <166543345606.23830.3120625408601531368.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2022 20:30:28.3244 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 49ad2eae-22fa-4de3-94e0-08daaafe4516 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT046.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB7006 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The current event configuration can be changed by the user by writing to the configuration file /sys/fs/resctrl/info/L3_MON/mbm_local_config. The event configuration settings are domain specific. Changing the configuration on one CPU in a domain would affect the whole domain. Following are the types of events supported: =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Bits Description =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D 6 Dirty Victims from the QOS domain to all types of memory 5 Reads to slow memory in the non-local NUMA domain 4 Reads to slow memory in the local NUMA domain 3 Non-temporal writes to non-local NUMA domain 2 Non-temporal writes to local NUMA domain 1 Reads to memory in the non-local NUMA domain 0 Reads to memory in the local NUMA domain =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D For example: To change the mbm_local_bytes to count all the non-temporal writes on domain 0. To achieve this, the bits 2 and 3 needs to be set which is 1100b (in hex 0xc). Run the command. $echo 0=3D0xc > /sys/fs/resctrl/info/L3_MON/mbm_local_config To change the mbm_local_bytes to count only reads to local NUMA domain 1. To achieve this, the bit 0 needs to be set which 1b (in hex 0x1). Run the command. $echo 1=3D0x1 > /sys/fs/resctrl/info/L3_MON/mbm_local_config Signed-off-by: Babu Moger --- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 25ff56ecb817..e744db5dc057 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1639,6 +1639,26 @@ static ssize_t mbm_total_config_write(struct kernfs_= open_file *of, return ret ?: nbytes; } =20 +static ssize_t mbm_local_config_write(struct kernfs_open_file *of, + char *buf, size_t nbytes, + loff_t off) +{ + struct rdt_resource *r =3D of->kn->parent->priv; + int ret; + + /* Valid input requires a trailing newline */ + if (nbytes =3D=3D 0 || buf[nbytes - 1] !=3D '\n') + return -EINVAL; + + rdt_last_cmd_clear(); + + buf[nbytes - 1] =3D '\0'; + + ret =3D mon_config_parse(r, buf, QOS_L3_MBM_LOCAL_EVENT_ID); + + return ret ?: nbytes; +} + /* rdtgroup information files for one cache resource. */ static struct rftype res_common_files[] =3D { { @@ -1749,6 +1769,7 @@ static struct rftype res_common_files[] =3D { .mode =3D 0644, .kf_ops =3D &rdtgroup_kf_single_ops, .seq_show =3D mbm_local_config_show, + .write =3D mbm_local_config_write, }, { .name =3D "cpus", From nobody Tue Apr 7 03:32:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 822CEC433FE for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT039.mail.protection.outlook.com (10.13.172.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5709.10 via Frontend Transport; Mon, 10 Oct 2022 20:30:35 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Mon, 10 Oct 2022 15:30:33 -0500 Subject: [PATCH v6 11/12] x86/resctrl: Replace smp_call_function_many() with on_each_cpu_mask() From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Mon, 10 Oct 2022 15:30:33 -0500 Message-ID: <166543383308.23830.18388408549121180741.stgit@bmoger-ubuntu> In-Reply-To: <166543345606.23830.3120625408601531368.stgit@bmoger-ubuntu> References: <166543345606.23830.3120625408601531368.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2022 20:30:35.6813 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 58904a36-670b-48e2-ed6c-08daaafe497d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT039.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4522 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The call on_each_cpu_mask() can run the function on each CPU specified by cpumask, which may include the local processor. So, replace the call smp_call_function_many() with on_each_cpu_mask() to simplify the code. Signed-off-by: Babu Moger --- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 29 ++++++++--------------------- 1 file changed, 8 insertions(+), 21 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index e744db5dc057..4f8a1c9c3e7a 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -325,12 +325,7 @@ static void update_cpu_closid_rmid(void *info) static void update_closid_rmid(const struct cpumask *cpu_mask, struct rdtgroup *r) { - int cpu =3D get_cpu(); - - if (cpumask_test_cpu(cpu, cpu_mask)) - update_cpu_closid_rmid(r); - smp_call_function_many(cpu_mask, update_cpu_closid_rmid, r, 1); - put_cpu(); + on_each_cpu_mask(cpu_mask, update_cpu_closid_rmid, r, 1); } =20 static int cpus_mon_write(struct rdtgroup *rdtgrp, cpumask_var_t newmask, @@ -2131,13 +2126,9 @@ static int set_cache_qos_cfg(int level, bool enable) /* Pick one CPU from each domain instance to update MSR */ cpumask_set_cpu(cpumask_any(&d->cpu_mask), cpu_mask); } - cpu =3D get_cpu(); - /* Update QOS_CFG MSR on this cpu if it's in cpu_mask. */ - if (cpumask_test_cpu(cpu, cpu_mask)) - update(&enable); - /* Update QOS_CFG MSR on all other cpus in cpu_mask. */ - smp_call_function_many(cpu_mask, update, &enable, 1); - put_cpu(); + + /* Update QOS_CFG MSR on all the CPUs in cpu_mask */ + on_each_cpu_mask(cpu_mask, update, &enable, 1); =20 free_cpumask_var(cpu_mask); =20 @@ -2614,7 +2605,7 @@ static int reset_all_ctrls(struct rdt_resource *r) struct msr_param msr_param; cpumask_var_t cpu_mask; struct rdt_domain *d; - int i, cpu; + int i; =20 if (!zalloc_cpumask_var(&cpu_mask, GFP_KERNEL)) return -ENOMEM; @@ -2635,13 +2626,9 @@ static int reset_all_ctrls(struct rdt_resource *r) for (i =3D 0; i < hw_res->num_closid; i++) hw_dom->ctrl_val[i] =3D r->default_ctrl; } - cpu =3D get_cpu(); - /* Update CBM on this cpu if it's in cpu_mask. */ - if (cpumask_test_cpu(cpu, cpu_mask)) - rdt_ctrl_update(&msr_param); - /* Update CBM on all other cpus in cpu_mask. */ - smp_call_function_many(cpu_mask, rdt_ctrl_update, &msr_param, 1); - put_cpu(); + + /* Update CBM on all the CPUs in cpu_mask */ + on_each_cpu_mask(cpu_mask, rdt_ctrl_update, &msr_param, 1); =20 free_cpumask_var(cpu_mask); =20 From nobody Tue Apr 7 03:32:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4BCE1C433F5 for ; Mon, 10 Oct 2022 20:32:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229931AbiJJUc3 (ORCPT ); Mon, 10 Oct 2022 16:32:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46012 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230292AbiJJUcC (ORCPT ); Mon, 10 Oct 2022 16:32:02 -0400 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2052.outbound.protection.outlook.com [40.107.93.52]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E7AE93EA67; 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Mon, 10 Oct 2022 20:30:43 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT072.mail.protection.outlook.com (10.13.173.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5709.10 via Frontend Transport; Mon, 10 Oct 2022 20:30:42 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Mon, 10 Oct 2022 15:30:40 -0500 Subject: [PATCH v6 12/12] Documentation/x86: Update resctrl_ui.rst for new features From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Mon, 10 Oct 2022 15:30:40 -0500 Message-ID: <166543384024.23830.1715326237069935949.stgit@bmoger-ubuntu> In-Reply-To: <166543345606.23830.3120625408601531368.stgit@bmoger-ubuntu> References: <166543345606.23830.3120625408601531368.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2022 20:30:42.8476 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e3c80a5e-513c-460d-cbd5-08daaafe4dc5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT072.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5794 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Update the documentation for the new features: 1. Slow Memory Bandwidth allocation (SMBA). With this feature, the QOS enforcement policies can be applied to the external slow memory connected to the host. QOS enforcement is accomplished by assigning a Class Of Service (COS) to a processor and specifying allocations or limits for that COS for each resource to be allocated. 2. Bandwidth Monitoring Event Configuration (BMEC). The bandwidth monitoring events mbm_total_bytes and mbm_local_bytes are set to count all the total and local reads/writes respectively. With the introduction of slow memory, the two counters are not enough to count all the different types of memory events. With the feature BMEC, the users have the option to configure mbm_total_bytes and mbm_local_bytes to count the specific type of events. Also add configuration instructions with examples. Signed-off-by: Babu Moger --- Documentation/x86/resctrl.rst | 136 +++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 134 insertions(+), 2 deletions(-) diff --git a/Documentation/x86/resctrl.rst b/Documentation/x86/resctrl.rst index 71a531061e4e..e2a59249d183 100644 --- a/Documentation/x86/resctrl.rst +++ b/Documentation/x86/resctrl.rst @@ -17,14 +17,16 @@ AMD refers to this feature as AMD Platform Quality of S= ervice(AMD QoS). This feature is enabled by the CONFIG_X86_CPU_RESCTRL and the x86 /proc/cp= uinfo flag bits: =20 -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D RDT (Resource Director Technology) Allocation "rdt_a" CAT (Cache Allocation Technology) "cat_l3", "cat_l2" CDP (Code and Data Prioritization) "cdp_l3", "cdp_l2" CQM (Cache QoS Monitoring) "cqm_llc", "cqm_occup_llc" MBM (Memory Bandwidth Monitoring) "cqm_mbm_total", "cqm_mbm_local" MBA (Memory Bandwidth Allocation) "mba" -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +SMBA (Slow Memory Bandwidth Allocation) "smba" +BMEC (Bandwidth Monitoring Event Configuration) "bmec" +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D =20 To use the feature mount the file system:: =20 @@ -161,6 +163,79 @@ with the following files: "mon_features": Lists the monitoring events if monitoring is enabled for the resource. + Example:: + + # cat /sys/fs/resctrl/info/L3_MON/mon_features + llc_occupancy + mbm_total_bytes + mbm_local_bytes + + If the system supports Bandwidth Monitoring Event + Configuration (BMEC), then the bandwidth events will + be configurable. The output will be:: + + # cat /sys/fs/resctrl/info/L3_MON/mon_features + llc_occupancy + mbm_total_bytes + mbm_total_config + mbm_local_bytes + mbm_local_config + +"mbm_total_config", "mbm_local_config": + These files contain the current event configuration for the events + mbm_total_bytes and mbm_local_bytes, respectively, when the + Bandwidth Monitoring Event Configuration (BMEC) feature is support= ed. + The event configuration settings are domain specific and will affe= ct + all the CPUs in the domain. + + Following are the types of events supported: + + =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + Bits Description + =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + 6 Dirty Victims from the QOS domain to all types of memory + 5 Reads to slow memory in the non-local NUMA domain + 4 Reads to slow memory in the local NUMA domain + 3 Non-temporal writes to non-local NUMA domain + 2 Non-temporal writes to local NUMA domain + 1 Reads to memory in the non-local NUMA domain + 0 Reads to memory in the local NUMA domain + =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + + By default, the mbm_total_bytes configuration is set to 0x7f to co= unt + all the event types and the mbm_local_bytes configuration is set to + 0x15 to count all the local memory events. + + Examples: + + * To view the current configuration:: + :: + + # cat /sys/fs/resctrl/info/L3_MON/mbm_total_config + 0=3D0x7f;1=3D0x7f;2=3D0x7f;3=3D0x7f + + # cat /sys/fs/resctrl/info/L3_MON/mbm_local_config + 0=3D0x15;1=3D0x15;3=3D0x15;4=3D0x15 + + * To change the mbm_total_bytes to count only reads on domain 0. + To achieve this, the bits 0, 1, 4 and 5 needs to be set which is + 110011b (in hex 0x33). + :: + + # echo "0=3D0x33" > /sys/fs/resctrl/info/L3_MON/mbm_total_con= fig + + # cat /sys/fs/resctrl/info/L3_MON/mbm_total_config + 0=3D0x33;1=3D0x7f;2=3D0x7f;3=3D0x7f + + * To change the mbm_local_bytes to count all the slow memory reads + on domain 1. To achieve this, the bits 4 and 5 needs to be set + which is 110000b (in hex 0x30). + :: + + # echo "1=3D0x30" > /sys/fs/resctrl/info/L3_MON/mbm_local_con= fig + + # cat /sys/fs/resctrl/info/L3_MON/mbm_local_config + 0=3D0x15;1=3D0x30;3=3D0x15;4=3D0x15 =20 "max_threshold_occupancy": Read/write file provides the largest value (in @@ -464,6 +539,25 @@ Memory bandwidth domain is L3 cache. =20 MB:=3Dbw_MBps0;=3Dbw_MBps1;... =20 +Slow Memory bandwidth Allocation (SMBA) +------------------------------------------------- +AMD hardware can support slow Memory bandwidth Allocation feature. +Currently, CXL.memory is the only supported "slow" memory device. +With the support of SMBA feature the hardware enables bandwidth +allocation on the slow memory devices. If there are multiple slow +memory devices in the system, then the throttling logic groups all +the slow sources together and applies the limit on them as a whole. + +The presence of the SMBA feature(with CXL.memory) is independent +of whether slow memory device is actually present in the system. +If there is no slow memory in the system, then setting a SMBA limit +will have no impact on the performance of the system. + +Slow Memory bandwidth domain is L3 cache. +:: + + SMBA:=3Dbandwidth0;=3Dbandwidth1;... + Reading/writing the schemata file --------------------------------- Reading the schemata file will show the state of all resources @@ -479,6 +573,44 @@ which you wish to change. E.g. L3DATA:0=3Dfffff;1=3Dfffff;2=3D3c0;3=3Dfffff L3CODE:0=3Dfffff;1=3Dfffff;2=3Dfffff;3=3Dfffff =20 +Reading/writing the schemata file (on AMD systems) +-------------------------------------------------- +Reading the schemata file will show the state of all resources +on all domains. When writing the memory bandwidth allocation you +only need to specify those values in an absolute number expressed +in 1/8 GB/s increments. To allocate bandwidth limit of 2GB, you +need to specify the value 16 (16 * 1/8 =3D 2). For example: +:: + + # cat schemata + MB:0=3D2048;1=3D2048;2=3D2048;3=3D2048 + L3:0=3Dffff;1=3Dffff;2=3Dffff;3=3Dffff + + # echo "MB:1=3D16" > schemata + # cat schemata + MB:0=3D2048;1=3D 16;2=3D2048;3=3D2048 + L3:0=3Dffff;1=3Dffff;2=3Dffff;3=3Dffff + +Reading/writing the schemata file (on AMD systems) with SMBA feature +------------------------------------------------------------------- +Reading the schemata file will show the state of all resources +on all domains. When writing the memory bandwidth allocation you +only need to specify those values in an absolute number expressed +in 1/8 GB/s increments. To allocate bandwidth limit of 8GB, you +need to specify the value 64 (64 * 1/8 =3D 8). E.g. +:: + + # cat schemata + SMBA:0=3D2048;1=3D2048;2=3D2048;3=3D2048 + MB:0=3D2048;1=3D2048;2=3D2048;3=3D2048 + L3:0=3Dffff;1=3Dffff;2=3Dffff;3=3Dffff + + # echo "SMBA:1=3D64" > schemata + # cat schemata + SMBA:0=3D2048;1=3D 64;2=3D2048;3=3D2048 + MB:0=3D2048;1=3D2048;2=3D2048;3=3D2048 + L3:0=3Dffff;1=3Dffff;2=3Dffff;3=3Dffff + Cache Pseudo-Locking =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D CAT enables a user to specify the amount of cache space that an