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Fri, 7 Oct 2022 02:51:13 -0700 From: Kartik To: , , , , , , , , , Subject: [PATCH 1/3] soc/tegra: fuse: use soc specific nvmem cells Date: Fri, 7 Oct 2022 15:21:06 +0530 Message-ID: <1665136268-29494-2-git-send-email-kkartik@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1665136268-29494-1-git-send-email-kkartik@nvidia.com> References: <1665136268-29494-1-git-send-email-kkartik@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT106:EE_|MW4PR12MB6899:EE_ X-MS-Office365-Filtering-Correlation-Id: e97cba46-09f7-43c8-5960-08daa8498388 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Foe4oPuZ8/RxKj2A6wRD5jywJv0so/eBEfz/aPOQjh9U4tmr4CEUqgs6diLhKeLHk9jxC52t5vY9wndgaTq8mNTtfiAK2jtLq1PkPsjYzHGsykPIt1+TU9xYha28T9SR5+OV2h2xx60qxiYZdZ8Q2kyj2HD7bL3dTJGvgc90KmlCwD6LvnUGujKmIIYRP/BlLPLhyKZ0QwO6R3PJlr094sScKJKODeMMVDihuUczN2dfySiS9J84pgVYbKuaFk2hvc78Zuf7stAPa3DuC7bFbJNjlUHCvy08y1uZPCaZGlNxmCYrwlvw3wlqqvh29D1W/CL0mxpG43F8rctiOwzIfJOz0NSKNG8GV7+/xruUfBezWWtGB2uIV/1yV/6GFLaoZjPiNz4zuGHRNfpiz/9MF2rixVMZAwu8tdNojTWh9XfjWcSSoRV3byaXDBBzZZpW+E73bzTu8fouz/81FF0m44z9PyO4s4CCIPIT7t/lbIASr8fxrBX3VI0FIDUwjlheAAUNX4wNPaKGYm0Wu2acPgS072BQPbU8ADgueiT3mRPbHDdbJI6Dirc37507stxvQGTd/CuXgbyqjOY2+UH17ySxSKPiQv+71kMBDAUmlHGKmM0XeZFHhKneLEGomfPwyUr/kQpAwwhohDYeIOrqB7YyRbzOikV3JVe0slWmBY31EDshFj78MQLLOPgS2WPOFsNam0Yo4is/B/RgEf0vOwmYm7K6FMcKYCMCkd2codhObc0OyRgTMGK6NAm3R8ezQZ3rKf6e1jBTEmDqODghoQSEXlGuTkdrwSj5L8NIVLY/Naz1LzdH/VcPumD7yBF6IBbPAUeU/X7KuuLoZA1i+Q== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(376002)(396003)(136003)(346002)(451199015)(46966006)(36840700001)(40470700004)(7696005)(6666004)(5660300002)(26005)(41300700001)(70206006)(8676002)(40480700001)(36756003)(336012)(921005)(47076005)(82740400003)(2616005)(426003)(83380400001)(356005)(7636003)(8936002)(30864003)(186003)(86362001)(82310400005)(40460700003)(70586007)(2906002)(478600001)(36860700001)(316002)(110136005)(83996005)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Oct 2022 09:51:31.7145 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e97cba46-09f7-43c8-5960-08daa8498388 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT106.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6899 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Tegra fuse block size, availability and offsets can vary from one SOC to another. Fix Tegra fuse size and use SOC specific nvmem cells. Signed-off-by: Kartik --- drivers/soc/tegra/fuse/fuse-tegra.c | 110 +----------- drivers/soc/tegra/fuse/fuse-tegra30.c | 240 +++++++++++++++++++++++++- drivers/soc/tegra/fuse/fuse.h | 2 + 3 files changed, 241 insertions(+), 111 deletions(-) diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/f= use-tegra.c index b0a8405dbdb19..cb97b59c2d89d 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra.c +++ b/drivers/soc/tegra/fuse/fuse-tegra.c @@ -94,112 +94,6 @@ static int tegra_fuse_read(void *priv, unsigned int off= set, void *value, return 0; } =20 -static const struct nvmem_cell_info tegra_fuse_cells[] =3D { - { - .name =3D "tsensor-cpu1", - .offset =3D 0x084, - .bytes =3D 4, - .bit_offset =3D 0, - .nbits =3D 32, - }, { - .name =3D "tsensor-cpu2", - .offset =3D 0x088, - .bytes =3D 4, - .bit_offset =3D 0, - .nbits =3D 32, - }, { - .name =3D "tsensor-cpu0", - .offset =3D 0x098, - .bytes =3D 4, - .bit_offset =3D 0, - .nbits =3D 32, - }, { - .name =3D "xusb-pad-calibration", - .offset =3D 0x0f0, - .bytes =3D 4, - .bit_offset =3D 0, - .nbits =3D 32, - }, { - .name =3D "tsensor-cpu3", - .offset =3D 0x12c, - .bytes =3D 4, - .bit_offset =3D 0, - .nbits =3D 32, - }, { - .name =3D "sata-calibration", - .offset =3D 0x124, - .bytes =3D 1, - .bit_offset =3D 0, - .nbits =3D 2, - }, { - .name =3D "tsensor-gpu", - .offset =3D 0x154, - .bytes =3D 4, - .bit_offset =3D 0, - .nbits =3D 32, - }, { - .name =3D "tsensor-mem0", - .offset =3D 0x158, - .bytes =3D 4, - .bit_offset =3D 0, - .nbits =3D 32, - }, { - .name =3D "tsensor-mem1", - .offset =3D 0x15c, - .bytes =3D 4, - .bit_offset =3D 0, - .nbits =3D 32, - }, { - .name =3D "tsensor-pllx", - .offset =3D 0x160, - .bytes =3D 4, - .bit_offset =3D 0, - .nbits =3D 32, - }, { - .name =3D "tsensor-common", - .offset =3D 0x180, - .bytes =3D 4, - .bit_offset =3D 0, - .nbits =3D 32, - }, { - .name =3D "gpu-gcplex-config-fuse", - .offset =3D 0x1c8, - .bytes =3D 4, - .bit_offset =3D 0, - .nbits =3D 32, - }, { - .name =3D "tsensor-realignment", - .offset =3D 0x1fc, - .bytes =3D 4, - .bit_offset =3D 0, - .nbits =3D 32, - }, { - .name =3D "gpu-calibration", - .offset =3D 0x204, - .bytes =3D 4, - .bit_offset =3D 0, - .nbits =3D 32, - }, { - .name =3D "xusb-pad-calibration-ext", - .offset =3D 0x250, - .bytes =3D 4, - .bit_offset =3D 0, - .nbits =3D 32, - }, { - .name =3D "gpu-pdi0", - .offset =3D 0x300, - .bytes =3D 4, - .bit_offset =3D 0, - .nbits =3D 32, - }, { - .name =3D "gpu-pdi1", - .offset =3D 0x304, - .bytes =3D 4, - .bit_offset =3D 0, - .nbits =3D 32, - }, -}; - static void tegra_fuse_restore(void *base) { fuse->base =3D (void __iomem *)base; @@ -253,8 +147,8 @@ static int tegra_fuse_probe(struct platform_device *pde= v) nvmem.name =3D "fuse"; nvmem.id =3D -1; nvmem.owner =3D THIS_MODULE; - nvmem.cells =3D tegra_fuse_cells; - nvmem.ncells =3D ARRAY_SIZE(tegra_fuse_cells); + nvmem.cells =3D fuse->soc->cells; + nvmem.ncells =3D fuse->soc->num_cells; nvmem.type =3D NVMEM_TYPE_OTP; nvmem.read_only =3D true; nvmem.root_only =3D true; diff --git a/drivers/soc/tegra/fuse/fuse-tegra30.c b/drivers/soc/tegra/fuse= /fuse-tegra30.c index f01d8a2547b6d..86547be567af0 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra30.c +++ b/drivers/soc/tegra/fuse/fuse-tegra30.c @@ -133,6 +133,82 @@ const struct tegra_fuse_soc tegra114_fuse_soc =3D { #endif =20 #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SO= C) +static const struct nvmem_cell_info tegra124_fuse_cells[] =3D { + { + .name =3D "tsensor-cpu1", + .offset =3D 0x084, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "tsensor-cpu2", + .offset =3D 0x088, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "tsensor-cpu0", + .offset =3D 0x098, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "xusb-pad-calibration", + .offset =3D 0x0f0, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "tsensor-cpu3", + .offset =3D 0x12c, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "sata-calibration", + .offset =3D 0x124, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "tsensor-gpu", + .offset =3D 0x154, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "tsensor-mem0", + .offset =3D 0x158, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "tsensor-mem1", + .offset =3D 0x15c, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "tsensor-pllx", + .offset =3D 0x160, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "tsensor-common", + .offset =3D 0x180, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "tsensor-realignment", + .offset =3D 0x1fc, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, +}; + static const struct nvmem_cell_lookup tegra124_fuse_lookups[] =3D { { .nvmem_name =3D "fuse", @@ -209,12 +285,96 @@ const struct tegra_fuse_soc tegra124_fuse_soc =3D { .info =3D &tegra124_fuse_info, .lookups =3D tegra124_fuse_lookups, .num_lookups =3D ARRAY_SIZE(tegra124_fuse_lookups), + .cells =3D tegra124_fuse_cells, + .num_cells =3D ARRAY_SIZE(tegra124_fuse_cells), .soc_attr_group =3D &tegra_soc_attr_group, .clk_suspend_on =3D true, }; #endif =20 #if defined(CONFIG_ARCH_TEGRA_210_SOC) +static const struct nvmem_cell_info tegra210_fuse_cells[] =3D { + { + .name =3D "tsensor-cpu1", + .offset =3D 0x084, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "tsensor-cpu2", + .offset =3D 0x088, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "tsensor-cpu0", + .offset =3D 0x098, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "xusb-pad-calibration", + .offset =3D 0x0f0, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "tsensor-cpu3", + .offset =3D 0x12c, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "sata-calibration", + .offset =3D 0x124, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "tsensor-gpu", + .offset =3D 0x154, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "tsensor-mem0", + .offset =3D 0x158, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "tsensor-mem1", + .offset =3D 0x15c, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "tsensor-pllx", + .offset =3D 0x160, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "tsensor-common", + .offset =3D 0x180, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "gpu-calibration", + .offset =3D 0x204, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "xusb-pad-calibration-ext", + .offset =3D 0x250, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, +}; + static const struct nvmem_cell_lookup tegra210_fuse_lookups[] =3D { { .nvmem_name =3D "fuse", @@ -295,6 +455,8 @@ const struct tegra_fuse_soc tegra210_fuse_soc =3D { .speedo_init =3D tegra210_init_speedo_data, .info =3D &tegra210_fuse_info, .lookups =3D tegra210_fuse_lookups, + .cells =3D tegra210_fuse_cells, + .num_cells =3D ARRAY_SIZE(tegra210_fuse_cells), .num_lookups =3D ARRAY_SIZE(tegra210_fuse_lookups), .soc_attr_group =3D &tegra_soc_attr_group, .clk_suspend_on =3D false, @@ -302,6 +464,22 @@ const struct tegra_fuse_soc tegra210_fuse_soc =3D { #endif =20 #if defined(CONFIG_ARCH_TEGRA_186_SOC) +static const struct nvmem_cell_info tegra186_fuse_cells[] =3D { + { + .name =3D "xusb-pad-calibration", + .offset =3D 0x0f0, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "xusb-pad-calibration-ext", + .offset =3D 0x250, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, +}; + static const struct nvmem_cell_lookup tegra186_fuse_lookups[] =3D { { .nvmem_name =3D "fuse", @@ -318,7 +496,7 @@ static const struct nvmem_cell_lookup tegra186_fuse_loo= kups[] =3D { =20 static const struct tegra_fuse_info tegra186_fuse_info =3D { .read =3D tegra30_fuse_read, - .size =3D 0x300, + .size =3D 0x478, .spare =3D 0x280, }; =20 @@ -327,12 +505,48 @@ const struct tegra_fuse_soc tegra186_fuse_soc =3D { .info =3D &tegra186_fuse_info, .lookups =3D tegra186_fuse_lookups, .num_lookups =3D ARRAY_SIZE(tegra186_fuse_lookups), + .cells =3D tegra186_fuse_cells, + .num_cells =3D ARRAY_SIZE(tegra186_fuse_cells), .soc_attr_group =3D &tegra_soc_attr_group, .clk_suspend_on =3D false, }; #endif =20 #if defined(CONFIG_ARCH_TEGRA_194_SOC) +static const struct nvmem_cell_info tegra194_fuse_cells[] =3D { + { + .name =3D "xusb-pad-calibration", + .offset =3D 0x0f0, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "gpu-gcplex-config-fuse", + .offset =3D 0x1c8, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "xusb-pad-calibration-ext", + .offset =3D 0x250, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "gpu-pdi0", + .offset =3D 0x300, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "gpu-pdi1", + .offset =3D 0x304, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, +}; + static const struct nvmem_cell_lookup tegra194_fuse_lookups[] =3D { { .nvmem_name =3D "fuse", @@ -364,7 +578,7 @@ static const struct nvmem_cell_lookup tegra194_fuse_loo= kups[] =3D { =20 static const struct tegra_fuse_info tegra194_fuse_info =3D { .read =3D tegra30_fuse_read, - .size =3D 0x300, + .size =3D 0x650, .spare =3D 0x280, }; =20 @@ -373,12 +587,30 @@ const struct tegra_fuse_soc tegra194_fuse_soc =3D { .info =3D &tegra194_fuse_info, .lookups =3D tegra194_fuse_lookups, .num_lookups =3D ARRAY_SIZE(tegra194_fuse_lookups), + .cells =3D tegra194_fuse_cells, + .num_cells =3D ARRAY_SIZE(tegra194_fuse_cells), .soc_attr_group =3D &tegra194_soc_attr_group, .clk_suspend_on =3D false, }; #endif =20 #if defined(CONFIG_ARCH_TEGRA_234_SOC) +static const struct nvmem_cell_info tegra234_fuse_cells[] =3D { + { + .name =3D "xusb-pad-calibration", + .offset =3D 0x0f0, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, { + .name =3D "xusb-pad-calibration-ext", + .offset =3D 0x250, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, + }, +}; + static const struct nvmem_cell_lookup tegra234_fuse_lookups[] =3D { { .nvmem_name =3D "fuse", @@ -395,7 +627,7 @@ static const struct nvmem_cell_lookup tegra234_fuse_loo= kups[] =3D { =20 static const struct tegra_fuse_info tegra234_fuse_info =3D { .read =3D tegra30_fuse_read, - .size =3D 0x300, + .size =3D 0x98c, .spare =3D 0x280, }; =20 @@ -404,6 +636,8 @@ const struct tegra_fuse_soc tegra234_fuse_soc =3D { .info =3D &tegra234_fuse_info, .lookups =3D tegra234_fuse_lookups, .num_lookups =3D ARRAY_SIZE(tegra234_fuse_lookups), + .cells =3D tegra234_fuse_cells, + .num_cells =3D ARRAY_SIZE(tegra234_fuse_cells), .soc_attr_group =3D &tegra194_soc_attr_group, .clk_suspend_on =3D false, }; diff --git a/drivers/soc/tegra/fuse/fuse.h b/drivers/soc/tegra/fuse/fuse.h index 2bb1f9d6a6e6d..02442157b231c 100644 --- a/drivers/soc/tegra/fuse/fuse.h +++ b/drivers/soc/tegra/fuse/fuse.h @@ -32,6 +32,8 @@ struct tegra_fuse_soc { =20 const struct nvmem_cell_lookup *lookups; unsigned int num_lookups; + const struct nvmem_cell_info *cells; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Oct 2022 09:51:26.9089 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 800125be-d3c4-4590-1308-08daa84980ab X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT080.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6091 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Tegra186 onwards, various fuse offsets are restricted and cannot be accessed from CCPLEX. Currently nvmem binary interface allows reading such offsets from userspace, which results in RAS errors. Add nvmem keepout lists to avoid any reads to restricted offsets. Signed-off-by: Kartik --- drivers/soc/tegra/fuse/fuse-tegra.c | 2 ++ drivers/soc/tegra/fuse/fuse-tegra30.c | 38 +++++++++++++++++++++++++++ drivers/soc/tegra/fuse/fuse.h | 2 ++ 3 files changed, 42 insertions(+) diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/f= use-tegra.c index cb97b59c2d89d..a68f36e1cab8f 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra.c +++ b/drivers/soc/tegra/fuse/fuse-tegra.c @@ -149,6 +149,8 @@ static int tegra_fuse_probe(struct platform_device *pde= v) nvmem.owner =3D THIS_MODULE; nvmem.cells =3D fuse->soc->cells; nvmem.ncells =3D fuse->soc->num_cells; + nvmem.keepout =3D fuse->soc->keepouts; + nvmem.nkeepout =3D fuse->soc->num_keepouts; nvmem.type =3D NVMEM_TYPE_OTP; nvmem.read_only =3D true; nvmem.root_only =3D true; diff --git a/drivers/soc/tegra/fuse/fuse-tegra30.c b/drivers/soc/tegra/fuse= /fuse-tegra30.c index 86547be567af0..932a03c64534a 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra30.c +++ b/drivers/soc/tegra/fuse/fuse-tegra30.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -494,6 +495,14 @@ static const struct nvmem_cell_lookup tegra186_fuse_lo= okups[] =3D { }, }; =20 +static const struct nvmem_keepout tegra186_fuse_keepouts[] =3D { + { .start =3D 0x01c, .end =3D 0x0f0 }, + { .start =3D 0x138, .end =3D 0x198 }, + { .start =3D 0x1d8, .end =3D 0x250 }, + { .start =3D 0x280, .end =3D 0x290 }, + { .start =3D 0x340, .end =3D 0x344 } +}; + static const struct tegra_fuse_info tegra186_fuse_info =3D { .read =3D tegra30_fuse_read, .size =3D 0x478, @@ -507,6 +516,8 @@ const struct tegra_fuse_soc tegra186_fuse_soc =3D { .num_lookups =3D ARRAY_SIZE(tegra186_fuse_lookups), .cells =3D tegra186_fuse_cells, .num_cells =3D ARRAY_SIZE(tegra186_fuse_cells), + .keepouts =3D tegra186_fuse_keepouts, + .num_keepouts =3D ARRAY_SIZE(tegra186_fuse_keepouts), .soc_attr_group =3D &tegra_soc_attr_group, .clk_suspend_on =3D false, }; @@ -576,6 +587,15 @@ static const struct nvmem_cell_lookup tegra194_fuse_lo= okups[] =3D { }, }; =20 +static const struct nvmem_keepout tegra194_fuse_keepouts[] =3D { + { .start =3D 0x01c, .end =3D 0x0b8 }, + { .start =3D 0x12c, .end =3D 0x198 }, + { .start =3D 0x1a0, .end =3D 0x1bc }, + { .start =3D 0x1d8, .end =3D 0x250 }, + { .start =3D 0x270, .end =3D 0x290 }, + { .start =3D 0x310, .end =3D 0x45c } +}; + static const struct tegra_fuse_info tegra194_fuse_info =3D { .read =3D tegra30_fuse_read, .size =3D 0x650, @@ -589,6 +609,8 @@ const struct tegra_fuse_soc tegra194_fuse_soc =3D { .num_lookups =3D ARRAY_SIZE(tegra194_fuse_lookups), .cells =3D tegra194_fuse_cells, .num_cells =3D ARRAY_SIZE(tegra194_fuse_cells), + .keepouts =3D tegra194_fuse_keepouts, + .num_keepouts =3D ARRAY_SIZE(tegra194_fuse_keepouts), .soc_attr_group =3D &tegra194_soc_attr_group, .clk_suspend_on =3D false, }; @@ -625,6 +647,20 @@ static const struct nvmem_cell_lookup tegra234_fuse_lo= okups[] =3D { }, }; =20 +static const struct nvmem_keepout tegra234_fuse_keepouts[] =3D { + { .start =3D 0x01c, .end =3D 0x0c8 }, + { .start =3D 0x12c, .end =3D 0x184 }, + { .start =3D 0x190, .end =3D 0x198 }, + { .start =3D 0x1a0, .end =3D 0x204 }, + { .start =3D 0x21c, .end =3D 0x250 }, + { .start =3D 0x25c, .end =3D 0x2f0 }, + { .start =3D 0x310, .end =3D 0x3d8 }, + { .start =3D 0x400, .end =3D 0x4f0 }, + { .start =3D 0x4f8, .end =3D 0x7e8 }, + { .start =3D 0x8d0, .end =3D 0x8d8 }, + { .start =3D 0xacc, .end =3D 0xf00 } +}; + static const struct tegra_fuse_info tegra234_fuse_info =3D { .read =3D tegra30_fuse_read, .size =3D 0x98c, @@ -638,6 +674,8 @@ const struct tegra_fuse_soc tegra234_fuse_soc =3D { .num_lookups =3D ARRAY_SIZE(tegra234_fuse_lookups), .cells =3D tegra234_fuse_cells, .num_cells =3D ARRAY_SIZE(tegra234_fuse_cells), + .keepouts =3D tegra234_fuse_keepouts, + .num_keepouts =3D ARRAY_SIZE(tegra234_fuse_keepouts), .soc_attr_group =3D &tegra194_soc_attr_group, .clk_suspend_on =3D false, }; diff --git a/drivers/soc/tegra/fuse/fuse.h b/drivers/soc/tegra/fuse/fuse.h index 02442157b231c..90f23be738947 100644 --- a/drivers/soc/tegra/fuse/fuse.h +++ b/drivers/soc/tegra/fuse/fuse.h @@ -34,6 +34,8 @@ struct tegra_fuse_soc { unsigned int num_lookups; const struct nvmem_cell_info *cells; unsigned int num_cells; + const struct nvmem_keepout *keepouts; + unsigned int num_keepouts; =20 const struct attribute_group *soc_attr_group; =20 --=20 2.17.1 From nobody Mon Apr 6 22:49:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50DBBC433FE for ; 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Fri, 7 Oct 2022 02:51:20 -0700 From: Kartik To: , , , , , , , , , Subject: [PATCH 3/3] soc/tegra: fuse: add opt-dla-disable nvmem cell Date: Fri, 7 Oct 2022 15:21:08 +0530 Message-ID: <1665136268-29494-4-git-send-email-kkartik@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1665136268-29494-1-git-send-email-kkartik@nvidia.com> References: <1665136268-29494-1-git-send-email-kkartik@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT106:EE_|SA1PR12MB5657:EE_ X-MS-Office365-Filtering-Correlation-Id: 18398717-e322-4258-8a78-08daa8498672 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 55b2B1+LMt/itKwoaQjEERznOgDpG1zav4HRbncUnRhY5vdO0G5T505GV1N+NeS/iQHMDgHh43KH+25J4YRQXlFsEV07v1Ya+r5Tf/YZmW0RZPqAODEsPhSlCK4K3NwuhsWz8q7lWYqiwkyTZcgZ2Swz1IdSfrMHDjOhBj2yHHZJ1C7EVToOdB2TjTh/YJSZlv+ALGy6oObHeMRQ/9/fZMjYs8KRDHOu6e7hXDV8nlRaWoxl1Px9wFpQgmQpZ2g1ku+qXLlrUsorsZgrOB4bmqp6/zwbhB5/9w3UZq0WIo4olqA0YSDwAiu96IAMnQz3nPsHpqKHK0avgbt9lyaSzYDM1U73sF23llkT7TxD+iyrEFvvCqw1BJx1uGw1IwVCAEuK1afKnYxwsZlNn3JuvwxRRhvKe8zGHLN5cM/XjL+L7/aJpyb37rvtl30Pjkdlfe/Z/bYAnFCXYBRd4SrKs13xshKN9MiYMuIvj5huPY6y3qouWoN3VLzRGA8esWxbbF0/HSYi6hTiYJEMfk8v7oiN/7USSF3luou9VkyTab/IzAGtWfn19MN2mr02Ssr1nNNfxt23fKhDfejsl3YCo/OU9KwjQHgYEejA7xN61oICWkq7PZL6fdwmTXKs9JkfASu/Tl5SLkYZ1NKjsVMsEL6A+msRAmxkIjHYGjlY39ZtmCdtHm4gFG3jdUhk/7GXWPFmxEmjCeBZgS5SEkZrCyXscXLb0QTkqyWwEf/VuGvcBg7q8TNUQ8U9+8XAN1WkkWExFl2nChthQos0yv4C2XfZokKvfSPp88TVrVceoX6yFxIjZ5ehnvs6yPPtN9nfjiLIA/eCBSYH2CtY/hnrIw== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(396003)(39860400002)(346002)(376002)(136003)(451199015)(46966006)(40470700004)(36840700001)(6666004)(70206006)(8676002)(86362001)(82310400005)(40460700003)(7696005)(70586007)(36860700001)(82740400003)(921005)(40480700001)(336012)(356005)(2616005)(186003)(478600001)(36756003)(2906002)(26005)(316002)(7636003)(8936002)(47076005)(426003)(110136005)(83380400001)(41300700001)(5660300002)(2101003)(83996005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Oct 2022 09:51:36.6204 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 18398717-e322-4258-8a78-08daa8498672 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT106.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB5657 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Tegra234 DLA (Deep Learning Accelerator) driver requires access to opt_dla_disable fuse to correctly identify internal or production boards. Add nvmem cell "opt-dla-disable" for Tegra234 SOC, this allows DLA driver to read opt_dla_disable fuse via nvmem interface. Signed-off-by: Kartik --- drivers/soc/tegra/fuse/fuse-tegra30.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/soc/tegra/fuse/fuse-tegra30.c b/drivers/soc/tegra/fuse= /fuse-tegra30.c index 932a03c64534a..0ee907af655b3 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra30.c +++ b/drivers/soc/tegra/fuse/fuse-tegra30.c @@ -630,6 +630,12 @@ static const struct nvmem_cell_info tegra234_fuse_cell= s[] =3D { .bytes =3D 4, .bit_offset =3D 0, .nbits =3D 32, + }, { + .name =3D "opt-dla-disable", + .offset =3D 0x3f0, + .bytes =3D 4, + .bit_offset =3D 0, + .nbits =3D 32, }, }; =20 @@ -644,6 +650,16 @@ static const struct nvmem_cell_lookup tegra234_fuse_lo= okups[] =3D { .cell_name =3D "xusb-pad-calibration-ext", .dev_id =3D "3520000.padctl", .con_id =3D "calibration-ext", + }, { + .nvmem_name =3D "fuse", + .cell_name =3D "opt-dla-disable", + .dev_id =3D "15880000.nvdla0", + .con_id =3D "dla-disable", + }, { + .nvmem_name =3D "fuse", + .cell_name =3D "opt-dla-disable", + .dev_id =3D "158c0000.nvdla1", + .con_id =3D "dla-disable", }, }; =20 --=20 2.17.1