From nobody Mon Apr 6 16:28:11 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE808C433FE for ; Tue, 4 Oct 2022 09:31:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231271AbiJDJbl (ORCPT ); Tue, 4 Oct 2022 05:31:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52124 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229764AbiJDJ1z (ORCPT ); Tue, 4 Oct 2022 05:27:55 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 59F7A11176; Tue, 4 Oct 2022 02:27:24 -0700 (PDT) Date: Tue, 04 Oct 2022 09:27:21 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1664875643; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6i+DxbJm/doHi/BHp8YQeKiqR1C8kCGmcZdL7hAEQK8=; b=vsKJA24qxoxw0p2vj4ca/WrnDTRcFYyD5rgdK/mHbh0QUBaTtdIiph4NDCWhSkhHQLYLxn F5OR8u9dh+B0zyjE4T8+uXsknIChEQ9L5uNK3O6KBMcecpUOoXfrTPb+BgGUsI9PyE5exE aUvAGFCzOrYBso/6EC1nsjyGKVnppcRFyUXNG9RaLDPJVM/eoryWuv4FwrsS+olT/fvJvg ExW0FZf/AkpklNOV9U4PXLIB10Sar+8YiDJoGjF8KzM1masDkifoyDN0yk7w5FU3FOEcip v7EpAsUkGu46fNaGn+/79USeXeQU9jDJ+SxYZsEBC2q9vGX9oppgI2ONAsxenw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1664875643; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6i+DxbJm/doHi/BHp8YQeKiqR1C8kCGmcZdL7hAEQK8=; b=Pryac6F4Tq8b2K3oe6CnDq63sSe5tUrvpi8f1xk47BGsOhSV80LYcEnKajqvUglYT3KxOP NmMsklYwn3f1YHCQ== From: "tip-bot2 for Vincent Whitchurch" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: timers/core] clocksource/drivers/exynos_mct: Support local-timers property Cc: Vincent Whitchurch , Krzysztof Kozlowski , Daniel Lezcano , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20220609112738.359385-4-vincent.whitchurch@axis.com> References: <20220609112738.359385-4-vincent.whitchurch@axis.com> MIME-Version: 1.0 Message-ID: <166487564166.401.1467190955976259089.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the timers/core branch of tip: Commit-ID: 47dbe4eb9822208be2b7ec901c7e0c15536f9c92 Gitweb: https://git.kernel.org/tip/47dbe4eb9822208be2b7ec901c7e0c155= 36f9c92 Author: Vincent Whitchurch AuthorDate: Thu, 09 Jun 2022 13:27:37 +02:00 Committer: Daniel Lezcano CommitterDate: Tue, 20 Sep 2022 10:49:45 +02:00 clocksource/drivers/exynos_mct: Support local-timers property If the device tree indicates that the hardware requires that the processor only use certain local timers, respect that. Signed-off-by: Vincent Whitchurch Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220609112738.359385-4-vincent.whitchurch@= axis.com Signed-off-by: Daniel Lezcano --- drivers/clocksource/exynos_mct.c | 62 ++++++++++++++++++++++++++++--- 1 file changed, 56 insertions(+), 6 deletions(-) diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_= mct.c index 1202383..bfd6009 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -33,7 +33,7 @@ #define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248) #define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C) #define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300) -#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x)) +#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * (x))) #define EXYNOS4_MCT_L_MASK (0xffffff00) =20 #define MCT_L_TCNTB_OFFSET (0x00) @@ -66,6 +66,8 @@ #define MCT_L0_IRQ 4 /* Max number of IRQ as per DT binding document */ #define MCT_NR_IRQS 20 +/* Max number of local timers */ +#define MCT_NR_LOCAL (MCT_NR_IRQS - MCT_L0_IRQ) =20 enum { MCT_INT_SPI, @@ -456,7 +458,6 @@ static int exynos4_mct_starting_cpu(unsigned int cpu) per_cpu_ptr(&percpu_mct_tick, cpu); struct clock_event_device *evt =3D &mevt->evt; =20 - mevt->base =3D EXYNOS4_MCT_L_BASE(cpu); snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu); =20 evt->name =3D mevt->name; @@ -527,8 +528,17 @@ static int __init exynos4_timer_resources(struct devic= e_node *np) return 0; } =20 +/** + * exynos4_timer_interrupts - initialize MCT interrupts + * @np: device node for MCT + * @int_type: interrupt type, MCT_INT_PPI or MCT_INT_SPI + * @local_idx: array mapping CPU numbers to local timer indices + * @nr_local: size of @local_idx array + */ static int __init exynos4_timer_interrupts(struct device_node *np, - unsigned int int_type) + unsigned int int_type, + const u32 *local_idx, + size_t nr_local) { int nr_irqs, i, err, cpu; =20 @@ -561,13 +571,21 @@ static int __init exynos4_timer_interrupts(struct dev= ice_node *np, } else { for_each_possible_cpu(cpu) { int mct_irq; + unsigned int irq_idx; struct mct_clock_event_device *pcpu_mevt =3D per_cpu_ptr(&percpu_mct_tick, cpu); =20 + if (cpu >=3D nr_local) { + err =3D -EINVAL; + goto out_irq; + } + + irq_idx =3D MCT_L0_IRQ + local_idx[cpu]; + pcpu_mevt->evt.irq =3D -1; - if (MCT_L0_IRQ + cpu >=3D ARRAY_SIZE(mct_irqs)) + if (irq_idx >=3D ARRAY_SIZE(mct_irqs)) break; - mct_irq =3D mct_irqs[MCT_L0_IRQ + cpu]; + mct_irq =3D mct_irqs[irq_idx]; =20 irq_set_status_flags(mct_irq, IRQ_NOAUTOEN); if (request_irq(mct_irq, @@ -583,6 +601,17 @@ static int __init exynos4_timer_interrupts(struct devi= ce_node *np, } } =20 + for_each_possible_cpu(cpu) { + struct mct_clock_event_device *mevt =3D per_cpu_ptr(&percpu_mct_tick, cp= u); + + if (cpu >=3D nr_local) { + err =3D -EINVAL; + goto out_irq; + } + + mevt->base =3D EXYNOS4_MCT_L_BASE(local_idx[cpu]); + } + /* Install hotplug callbacks which configure the timer on this CPU */ err =3D cpuhp_setup_state(CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING, "clockevents/exynos4/mct_timer:starting", @@ -613,13 +642,34 @@ out_irq: static int __init mct_init_dt(struct device_node *np, unsigned int int_typ= e) { bool frc_shared =3D of_property_read_bool(np, "samsung,frc-shared"); + u32 local_idx[MCT_NR_LOCAL] =3D {0}; + int nr_local; int ret; =20 + nr_local =3D of_property_count_u32_elems(np, "samsung,local-timers"); + if (nr_local =3D=3D 0) + return -EINVAL; + if (nr_local > 0) { + if (nr_local > ARRAY_SIZE(local_idx)) + return -EINVAL; + + ret =3D of_property_read_u32_array(np, "samsung,local-timers", + local_idx, nr_local); + if (ret) + return ret; + } else { + int i; + + nr_local =3D ARRAY_SIZE(local_idx); + for (i =3D 0; i < nr_local; i++) + local_idx[i] =3D i; + } + ret =3D exynos4_timer_resources(np); if (ret) return ret; =20 - ret =3D exynos4_timer_interrupts(np, int_type); + ret =3D exynos4_timer_interrupts(np, int_type, local_idx, nr_local); if (ret) return ret;