From nobody Sun May 5 02:46:38 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87834C4332F for ; Thu, 29 Sep 2022 16:28:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236196AbiI2Q1u (ORCPT ); Thu, 29 Sep 2022 12:27:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34050 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235682AbiI2Q1I (ORCPT ); Thu, 29 Sep 2022 12:27:08 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7E81113AF3E for ; Thu, 29 Sep 2022 09:26:23 -0700 (PDT) Date: Thu, 29 Sep 2022 16:26:20 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1664468782; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jT/fssExa+XkLZZok5Z/qvXpk2Zv8JuhGNmtrqOnM9g=; b=W4s2idtX07qQGchFR+wy1JsafYG2JgNMEAzawrML/HfLjPyjZ0+FRZir9cHNiJAj4RyYQ/ ia1mtXBD4/0GSahaDRSJmufPqTesjy+Sla2FfA423gnVO9mS+AumCsH6ZJnfeWAvVDjA+n XQfjAUUUiGx6DBBVlOpTZOD22yHH2hySi09d9z6zAT6jLt0haygL1/Og31xz2PuQTPWaaX C4TbKqw9DfWru7FIgvNhbOG5eeR6FsraVult08CRozvYzoYbIQO6wux033o527F68On/Hv 4aXPTvYaebFZIeNEsCyOk8RcwxNyenRfDvpWfYZ9crT/YO7Ytm6UfTNpoS0EtQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1664468782; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jT/fssExa+XkLZZok5Z/qvXpk2Zv8JuhGNmtrqOnM9g=; b=MX2LntJvfFMF1GRneYx6qWq+uyJjSvSRfQOFyRoEzw+DIZd6Fill+tAIrqth7Gd4iPUa2Z /onYGnl/2lT3bsDQ== From: "irqchip-bot for Frank Li" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-kernel@vger.kernel.org Subject: [irqchip: irq/irqchip-next] irqchip: Add IMX MU MSI controller driver Cc: Frank Li , Marc Zyngier , tglx@linutronix.de In-Reply-To: <20220922161246.20586-4-Frank.Li@nxp.com> References: <20220922161246.20586-4-Frank.Li@nxp.com> MIME-Version: 1.0 Message-ID: <166446878078.401.7456525965900453888.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the irq/irqchip-next branch of ir= qchip: Commit-ID: 70afdab904d2d1e68bffe75fe08e7e48e0b0ff8e Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-plat= forms/70afdab904d2d1e68bffe75fe08e7e48e0b0ff8e Author: Frank Li AuthorDate: Thu, 22 Sep 2022 11:12:43 -05:00 Committer: Marc Zyngier CommitterDate: Thu, 29 Sep 2022 17:11:37 +01:00 irqchip: Add IMX MU MSI controller driver The MU block found in a number of Freescale/NXP SoCs supports generating IRQs by writing data to a register. This enables the MU block to be used as a MSI controller, by leveraging the platform-MSI API. Signed-off-by: Frank Li [maz: dropped pointless dma-iommu.h and of_pci.h includes] Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20220922161246.20586-4-Frank.Li@nxp.com --- drivers/irqchip/Kconfig | 14 +- drivers/irqchip/Makefile | 1 +- drivers/irqchip/irq-imx-mu-msi.c | 453 ++++++++++++++++++++++++++++++- 3 files changed, 468 insertions(+) create mode 100644 drivers/irqchip/irq-imx-mu-msi.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 66b9fa4..a213465 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -481,6 +481,20 @@ config IMX_INTMUX help Support for the i.MX INTMUX interrupt multiplexer. =20 +config IMX_MU_MSI + tristate "i.MX MU used as MSI controller" + depends on OF && HAS_IOMEM + default m if ARCH_MXC + select IRQ_DOMAIN + select IRQ_DOMAIN_HIERARCHY + select GENERIC_MSI_IRQ_DOMAIN + help + Provide a driver for the MU block used as a CPU-to-CPU MSI + controller. This requires a specially crafted DT to make use + of this driver. + + If unsure, say N + config LS1X_IRQ bool "Loongson-1 Interrupt Controller" depends on MACH_LOONGSON32 diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index b6acbca..87b49a1 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -99,6 +99,7 @@ obj-$(CONFIG_RISCV_INTC) +=3D irq-riscv-intc.o obj-$(CONFIG_SIFIVE_PLIC) +=3D irq-sifive-plic.o obj-$(CONFIG_IMX_IRQSTEER) +=3D irq-imx-irqsteer.o obj-$(CONFIG_IMX_INTMUX) +=3D irq-imx-intmux.o +obj-$(CONFIG_IMX_MU_MSI) +=3D irq-imx-mu-msi.o obj-$(CONFIG_MADERA_IRQ) +=3D irq-madera.o obj-$(CONFIG_LS1X_IRQ) +=3D irq-ls1x.o obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) +=3D irq-ti-sci-intr.o diff --git a/drivers/irqchip/irq-imx-mu-msi.c b/drivers/irqchip/irq-imx-mu-= msi.c new file mode 100644 index 0000000..b62139d --- /dev/null +++ b/drivers/irqchip/irq-imx-mu-msi.c @@ -0,0 +1,453 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Freescale MU used as MSI controller + * + * Copyright (c) 2018 Pengutronix, Oleksij Rempel + * Copyright 2022 NXP + * Frank Li + * Peng Fan + * + * Based on drivers/mailbox/imx-mailbox.c + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define IMX_MU_CHANS 4 + +enum imx_mu_xcr { + IMX_MU_GIER, + IMX_MU_GCR, + IMX_MU_TCR, + IMX_MU_RCR, + IMX_MU_xCR_MAX, +}; + +enum imx_mu_xsr { + IMX_MU_SR, + IMX_MU_GSR, + IMX_MU_TSR, + IMX_MU_RSR, + IMX_MU_xSR_MAX +}; + +enum imx_mu_type { + IMX_MU_V2 =3D BIT(1), +}; + +/* Receive Interrupt Enable */ +#define IMX_MU_xCR_RIEn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) := BIT(24 + (3 - (x)))) +#define IMX_MU_xSR_RFn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : = BIT(24 + (3 - (x)))) + +struct imx_mu_dcfg { + enum imx_mu_type type; + u32 xTR; /* Transmit Register0 */ + u32 xRR; /* Receive Register0 */ + u32 xSR[IMX_MU_xSR_MAX]; /* Status Registers */ + u32 xCR[IMX_MU_xCR_MAX]; /* Control Registers */ +}; + +struct imx_mu_msi { + raw_spinlock_t lock; + struct irq_domain *msi_domain; + void __iomem *regs; + phys_addr_t msiir_addr; + const struct imx_mu_dcfg *cfg; + unsigned long used; + struct clk *clk; +}; + +static void imx_mu_write(struct imx_mu_msi *msi_data, u32 val, u32 offs) +{ + iowrite32(val, msi_data->regs + offs); +} + +static u32 imx_mu_read(struct imx_mu_msi *msi_data, u32 offs) +{ + return ioread32(msi_data->regs + offs); +} + +static u32 imx_mu_xcr_rmw(struct imx_mu_msi *msi_data, enum imx_mu_xcr typ= e, u32 set, u32 clr) +{ + unsigned long flags; + u32 val; + + raw_spin_lock_irqsave(&msi_data->lock, flags); + val =3D imx_mu_read(msi_data, msi_data->cfg->xCR[type]); + val &=3D ~clr; + val |=3D set; + imx_mu_write(msi_data, val, msi_data->cfg->xCR[type]); + raw_spin_unlock_irqrestore(&msi_data->lock, flags); + + return val; +} + +static void imx_mu_msi_parent_mask_irq(struct irq_data *data) +{ + struct imx_mu_msi *msi_data =3D irq_data_get_irq_chip_data(data); + + imx_mu_xcr_rmw(msi_data, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(msi_data, data->h= wirq)); +} + +static void imx_mu_msi_parent_unmask_irq(struct irq_data *data) +{ + struct imx_mu_msi *msi_data =3D irq_data_get_irq_chip_data(data); + + imx_mu_xcr_rmw(msi_data, IMX_MU_RCR, IMX_MU_xCR_RIEn(msi_data, data->hwir= q), 0); +} + +static void imx_mu_msi_parent_ack_irq(struct irq_data *data) +{ + struct imx_mu_msi *msi_data =3D irq_data_get_irq_chip_data(data); + + imx_mu_read(msi_data, msi_data->cfg->xRR + data->hwirq * 4); +} + +static struct irq_chip imx_mu_msi_irq_chip =3D { + .name =3D "MU-MSI", + .irq_ack =3D irq_chip_ack_parent, +}; + +static struct msi_domain_ops imx_mu_msi_irq_ops =3D { +}; + +static struct msi_domain_info imx_mu_msi_domain_info =3D { + .flags =3D (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), + .ops =3D &imx_mu_msi_irq_ops, + .chip =3D &imx_mu_msi_irq_chip, +}; + +static void imx_mu_msi_parent_compose_msg(struct irq_data *data, + struct msi_msg *msg) +{ + struct imx_mu_msi *msi_data =3D irq_data_get_irq_chip_data(data); + u64 addr =3D msi_data->msiir_addr + 4 * data->hwirq; + + msg->address_hi =3D upper_32_bits(addr); + msg->address_lo =3D lower_32_bits(addr); + msg->data =3D data->hwirq; +} + +static int imx_mu_msi_parent_set_affinity(struct irq_data *irq_data, + const struct cpumask *mask, bool force) +{ + return -EINVAL; +} + +static struct irq_chip imx_mu_msi_parent_chip =3D { + .name =3D "MU", + .irq_mask =3D imx_mu_msi_parent_mask_irq, + .irq_unmask =3D imx_mu_msi_parent_unmask_irq, + .irq_ack =3D imx_mu_msi_parent_ack_irq, + .irq_compose_msi_msg =3D imx_mu_msi_parent_compose_msg, + .irq_set_affinity =3D imx_mu_msi_parent_set_affinity, +}; + +static int imx_mu_msi_domain_irq_alloc(struct irq_domain *domain, + unsigned int virq, + unsigned int nr_irqs, + void *args) +{ + struct imx_mu_msi *msi_data =3D domain->host_data; + unsigned long flags; + int pos, err =3D 0; + + WARN_ON(nr_irqs !=3D 1); + + raw_spin_lock_irqsave(&msi_data->lock, flags); + pos =3D find_first_zero_bit(&msi_data->used, IMX_MU_CHANS); + if (pos < IMX_MU_CHANS) + __set_bit(pos, &msi_data->used); + else + err =3D -ENOSPC; + raw_spin_unlock_irqrestore(&msi_data->lock, flags); + + if (err) + return err; + + irq_domain_set_info(domain, virq, pos, + &imx_mu_msi_parent_chip, msi_data, + handle_edge_irq, NULL, NULL); + return 0; +} + +static void imx_mu_msi_domain_irq_free(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs) +{ + struct irq_data *d =3D irq_domain_get_irq_data(domain, virq); + struct imx_mu_msi *msi_data =3D irq_data_get_irq_chip_data(d); + unsigned long flags; + + raw_spin_lock_irqsave(&msi_data->lock, flags); + __clear_bit(d->hwirq, &msi_data->used); + raw_spin_unlock_irqrestore(&msi_data->lock, flags); +} + +static const struct irq_domain_ops imx_mu_msi_domain_ops =3D { + .alloc =3D imx_mu_msi_domain_irq_alloc, + .free =3D imx_mu_msi_domain_irq_free, +}; + +static void imx_mu_msi_irq_handler(struct irq_desc *desc) +{ + struct imx_mu_msi *msi_data =3D irq_desc_get_handler_data(desc); + struct irq_chip *chip =3D irq_desc_get_chip(desc); + u32 status; + int i; + + status =3D imx_mu_read(msi_data, msi_data->cfg->xSR[IMX_MU_RSR]); + + chained_irq_enter(chip, desc); + for (i =3D 0; i < IMX_MU_CHANS; i++) { + if (status & IMX_MU_xSR_RFn(msi_data, i)) + generic_handle_domain_irq(msi_data->msi_domain, i); + } + chained_irq_exit(chip, desc); +} + +static int imx_mu_msi_domains_init(struct imx_mu_msi *msi_data, struct dev= ice *dev) +{ + struct fwnode_handle *fwnodes =3D dev_fwnode(dev); + struct irq_domain *parent; + + /* Initialize MSI domain parent */ + parent =3D irq_domain_create_linear(fwnodes, + IMX_MU_CHANS, + &imx_mu_msi_domain_ops, + msi_data); + if (!parent) { + dev_err(dev, "failed to create IRQ domain\n"); + return -ENOMEM; + } + + irq_domain_update_bus_token(parent, DOMAIN_BUS_NEXUS); + + msi_data->msi_domain =3D platform_msi_create_irq_domain(fwnodes, + &imx_mu_msi_domain_info, + parent); + + if (!msi_data->msi_domain) { + dev_err(dev, "failed to create MSI domain\n"); + irq_domain_remove(parent); + return -ENOMEM; + } + + irq_domain_set_pm_device(msi_data->msi_domain, dev); + + return 0; +} + +/* Register offset of different version MU IP */ +static const struct imx_mu_dcfg imx_mu_cfg_imx6sx =3D { + .type =3D 0, + .xTR =3D 0x0, + .xRR =3D 0x10, + .xSR =3D { + [IMX_MU_SR] =3D 0x20, + [IMX_MU_GSR] =3D 0x20, + [IMX_MU_TSR] =3D 0x20, + [IMX_MU_RSR] =3D 0x20, + }, + .xCR =3D { + [IMX_MU_GIER] =3D 0x24, + [IMX_MU_GCR] =3D 0x24, + [IMX_MU_TCR] =3D 0x24, + [IMX_MU_RCR] =3D 0x24, + }, +}; + +static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp =3D { + .type =3D 0, + .xTR =3D 0x20, + .xRR =3D 0x40, + .xSR =3D { + [IMX_MU_SR] =3D 0x60, + [IMX_MU_GSR] =3D 0x60, + [IMX_MU_TSR] =3D 0x60, + [IMX_MU_RSR] =3D 0x60, + }, + .xCR =3D { + [IMX_MU_GIER] =3D 0x64, + [IMX_MU_GCR] =3D 0x64, + [IMX_MU_TCR] =3D 0x64, + [IMX_MU_RCR] =3D 0x64, + }, +}; + +static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp =3D { + .type =3D IMX_MU_V2, + .xTR =3D 0x200, + .xRR =3D 0x280, + .xSR =3D { + [IMX_MU_SR] =3D 0xC, + [IMX_MU_GSR] =3D 0x118, + [IMX_MU_GSR] =3D 0x124, + [IMX_MU_RSR] =3D 0x12C, + }, + .xCR =3D { + [IMX_MU_GIER] =3D 0x110, + [IMX_MU_GCR] =3D 0x114, + [IMX_MU_TCR] =3D 0x120, + [IMX_MU_RCR] =3D 0x128 + }, +}; + +static int __init imx_mu_of_init(struct device_node *dn, + struct device_node *parent, + const struct imx_mu_dcfg *cfg) +{ + struct platform_device *pdev =3D of_find_device_by_node(dn); + struct device_link *pd_link_a; + struct device_link *pd_link_b; + struct imx_mu_msi *msi_data; + struct resource *res; + struct device *pd_a; + struct device *pd_b; + struct device *dev; + int ret; + int irq; + + dev =3D &pdev->dev; + + msi_data =3D devm_kzalloc(&pdev->dev, sizeof(*msi_data), GFP_KERNEL); + if (!msi_data) + return -ENOMEM; + + msi_data->cfg =3D cfg; + + msi_data->regs =3D devm_platform_ioremap_resource_byname(pdev, "processor= -a-side"); + if (IS_ERR(msi_data->regs)) { + dev_err(&pdev->dev, "failed to initialize 'regs'\n"); + return PTR_ERR(msi_data->regs); + } + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "processor-b-s= ide"); + if (!res) + return -EIO; + + msi_data->msiir_addr =3D res->start + msi_data->cfg->xTR; + + irq =3D platform_get_irq(pdev, 0); + if (irq <=3D 0) + return -ENODEV; + + platform_set_drvdata(pdev, msi_data); + + msi_data->clk =3D devm_clk_get(dev, NULL); + if (IS_ERR(msi_data->clk)) + return PTR_ERR(msi_data->clk); + + pd_a =3D dev_pm_domain_attach_by_name(dev, "processor-a-side"); + if (IS_ERR(pd_a)) + return PTR_ERR(pd_a); + + pd_b =3D dev_pm_domain_attach_by_name(dev, "processor-b-side"); + if (IS_ERR(pd_b)) + return PTR_ERR(pd_b); + + pd_link_a =3D device_link_add(dev, pd_a, + DL_FLAG_STATELESS | + DL_FLAG_PM_RUNTIME | + DL_FLAG_RPM_ACTIVE); + + if (!pd_link_a) { + dev_err(dev, "Failed to add device_link to mu a.\n"); + goto err_pd_a; + } + + pd_link_b =3D device_link_add(dev, pd_b, + DL_FLAG_STATELESS | + DL_FLAG_PM_RUNTIME | + DL_FLAG_RPM_ACTIVE); + + + if (!pd_link_b) { + dev_err(dev, "Failed to add device_link to mu a.\n"); + goto err_pd_b; + } + + ret =3D imx_mu_msi_domains_init(msi_data, dev); + if (ret) + goto err_dm_init; + + pm_runtime_enable(dev); + + irq_set_chained_handler_and_data(irq, + imx_mu_msi_irq_handler, + msi_data); + + return 0; + +err_dm_init: + device_link_remove(dev, pd_b); +err_pd_b: + device_link_remove(dev, pd_a); +err_pd_a: + return -EINVAL; +} + +static int __maybe_unused imx_mu_runtime_suspend(struct device *dev) +{ + struct imx_mu_msi *priv =3D dev_get_drvdata(dev); + + clk_disable_unprepare(priv->clk); + + return 0; +} + +static int __maybe_unused imx_mu_runtime_resume(struct device *dev) +{ + struct imx_mu_msi *priv =3D dev_get_drvdata(dev); + int ret; + + ret =3D clk_prepare_enable(priv->clk); + if (ret) + dev_err(dev, "failed to enable clock\n"); + + return ret; +} + +static const struct dev_pm_ops imx_mu_pm_ops =3D { + SET_RUNTIME_PM_OPS(imx_mu_runtime_suspend, + imx_mu_runtime_resume, NULL) +}; + +static int __init imx_mu_imx7ulp_of_init(struct device_node *dn, + struct device_node *parent) +{ + return imx_mu_of_init(dn, parent, &imx_mu_cfg_imx7ulp); +} + +static int __init imx_mu_imx6sx_of_init(struct device_node *dn, + struct device_node *parent) +{ + return imx_mu_of_init(dn, parent, &imx_mu_cfg_imx6sx); +} + +static int __init imx_mu_imx8ulp_of_init(struct device_node *dn, + struct device_node *parent) +{ + return imx_mu_of_init(dn, parent, &imx_mu_cfg_imx8ulp); +} + +IRQCHIP_PLATFORM_DRIVER_BEGIN(imx_mu_msi) +IRQCHIP_MATCH("fsl,imx7ulp-mu-msi", imx_mu_imx7ulp_of_init) +IRQCHIP_MATCH("fsl,imx6sx-mu-msi", imx_mu_imx6sx_of_init) +IRQCHIP_MATCH("fsl,imx8ulp-mu-msi", imx_mu_imx8ulp_of_init) +IRQCHIP_PLATFORM_DRIVER_END(imx_mu_msi, .pm =3D &imx_mu_pm_ops) + + +MODULE_AUTHOR("Frank Li "); +MODULE_DESCRIPTION("Freescale MU MSI controller driver"); +MODULE_LICENSE("GPL");