From nobody Sat May 4 06:29:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46533C32771 for ; Wed, 28 Sep 2022 13:37:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233993AbiI1NhX (ORCPT ); Wed, 28 Sep 2022 09:37:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45118 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233724AbiI1NhV (ORCPT ); Wed, 28 Sep 2022 09:37:21 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0C41E8E4E7 for ; Wed, 28 Sep 2022 06:37:17 -0700 (PDT) Date: Wed, 28 Sep 2022 13:37:13 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1664372235; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Vb2NAsuQMZeCWwgkNSMKDWzlnZ58auEKjch9Ob3ZsKQ=; b=mc+lHD+wHsowi0+b8FOi7phFsrl5317KjpOYUeTmzULLPv99NDDrNYY5pBPasjyS4DrPPk tSx56qouY0V8Y13tYIKipR9TyFH8vciJdNAUbp3CHV4bsYSnHBBHpmE+BfL/SSfQgJd4In 4CGn1hQul8AXD6NhM/mK2jpvMoDdy5nivt8ZWGUbsMW2ilZjqnczPC6kr+D7YW5tFU7gYW AvSmPcD1wMoxMvHqVH2bFMCro2ves9Upo0tmNnHaRtVyvCHKW2Nxk1iD7MdLrrNI+0MhKl jUSeEFc7fjLTn52Z0LbtV1BCmbC6Ejzx6/JdPzC+ntIx8680ZjyLbg1wDHulWA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1664372235; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Vb2NAsuQMZeCWwgkNSMKDWzlnZ58auEKjch9Ob3ZsKQ=; b=0orhfXPHcmet4WO31rOF1pvq8Z2AyLTZcmwljKEqtaHljQEKfVOPHKeLCySqHEtzoyB/Ai zswAfi1M0gAAVdAw== From: "irqchip-bot for Frank Li" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-kernel@vger.kernel.org Subject: [irqchip: irq/irqchip-next] dt-bindings: irqchip: Describe the IMX MU block as a MSI controller Cc: Rob Herring , Frank Li , Marc Zyngier , tglx@linutronix.de In-Reply-To: <20220922161246.20586-5-Frank.Li@nxp.com> References: <20220922161246.20586-5-Frank.Li@nxp.com> MIME-Version: 1.0 Message-ID: <166437223395.401.8077585689879090034.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the irq/irqchip-next branch of ir= qchip: Commit-ID: 27c0141e094e45e875ccc1f299458db6433c1e55 Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-plat= forms/27c0141e094e45e875ccc1f299458db6433c1e55 Author: Frank Li AuthorDate: Thu, 22 Sep 2022 11:12:44 -05:00 Committer: Marc Zyngier CommitterDate: Wed, 28 Sep 2022 14:24:32 +01:00 dt-bindings: irqchip: Describe the IMX MU block as a MSI controller I.MX MU supports generating IRQs by writing to a register. Describe its use as a MSI controller so that other blocks (such as a PCI EP) can use it directly. Reviewed-by: Rob Herring Signed-off-by: Frank Li [maz: commit message] Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20220922161246.20586-5-Frank.Li@nxp.com --- Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml | = 99 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 99 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= fsl,mu-msi.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-= msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-ms= i.yaml new file mode 100644 index 0000000..799ae5c --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale/NXP i.MX Messaging Unit (MU) work as msi controller + +maintainers: + - Frank Li + +description: | + The Messaging Unit module enables two processors within the SoC to + communicate and coordinate by passing messages (e.g. data, status + and control) through the MU interface. The MU also provides the ability + for one processor (A side) to signal the other processor (B side) using + interrupts. + + Because the MU manages the messaging between processors, the MU uses + different clocks (from each side of the different peripheral buses). + Therefore, the MU must synchronize the accesses from one side to the + other. The MU accomplishes synchronization using two sets of matching + registers (Processor A-side, Processor B-side). + + MU can work as msi interrupt controller to do doorbell + +allOf: + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + +properties: + compatible: + enum: + - fsl,imx6sx-mu-msi + - fsl,imx7ulp-mu-msi + - fsl,imx8ulp-mu-msi + - fsl,imx8ulp-mu-msi-s4 + + reg: + items: + - description: a side register base address + - description: b side register base address + + reg-names: + items: + - const: processor-a-side + - const: processor-b-side + + interrupts: + description: a side interrupt number. + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + items: + - description: a side power domain + - description: b side power domain + + power-domain-names: + items: + - const: processor-a-side + - const: processor-b-side + + interrupt-controller: true + + msi-controller: true + + "#msi-cells": + const: 0 + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - msi-controller + - "#msi-cells" + +additionalProperties: false + +examples: + - | + #include + #include + + msi-controller@5d270000 { + compatible =3D "fsl,imx6sx-mu-msi"; + msi-controller; + #msi-cells =3D <0>; + interrupt-controller; + reg =3D <0x5d270000 0x10000>, /* A side */ + <0x5d300000 0x10000>; /* B side */ + reg-names =3D "processor-a-side", "processor-b-side"; + interrupts =3D ; + power-domains =3D <&pd IMX_SC_R_MU_12A>, + <&pd IMX_SC_R_MU_12B>; + power-domain-names =3D "processor-a-side", "processor-b-side"; + };