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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT013.mail.protection.outlook.com (10.13.176.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5676.17 via Frontend Transport; Tue, 27 Sep 2022 20:25:35 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Tue, 27 Sep 2022 15:25:33 -0500 Subject: [PATCH v5 01/12] x86/cpufeatures: Add Slow Memory Bandwidth Allocation feature flag From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Tue, 27 Sep 2022 15:25:31 -0500 Message-ID: <166431033184.373387.6520785024194837522.stgit@bmoger-ubuntu> In-Reply-To: <166431016617.373387.1968875281081252467.stgit@bmoger-ubuntu> References: <166431016617.373387.1968875281081252467.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Sep 2022 20:25:35.7949 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a22bb6c5-efe0-450e-5f82-08daa0c66f5b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT013.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4494 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the new AMD feature X86_FEATURE_SMBA. With this feature, the QOS enforcement policies can be applied to external slow memory connected to the host. QOS enforcement is accomplished by assigning a Class Of Service (COS) to a processor and specifying allocations or limits for that COS for each resource to be allocated. This feature is identified by the CPUID Function 8000_0020_EBX_x0. CPUID Fn8000_0020_EBX_x0 AMD Bandwidth Enforcement Feature Identifiers (ECX=3D0) Bits Field Name Description 2 L3SBE L3 external slow memory bandwidth enforcement Currently, CXL.memory is the only supported "slow" memory device. With the support of SMBA feature, the hardware enables bandwidth allocation on the slow memory devices. If there are multiple slow memory devices in the system, then the throttling logic groups all the slow sources together and applies the limit on them as a whole. The presence of the SMBA feature(with CXL.memory) is independent of whether slow memory device is actually present in the system. If there is no slow memory in the system, then setting a SMBA limit will have no impact on the performance of the system. Presence of CXL memory can be identified by numactl command. $numactl -H available: 2 nodes (0-1) node 0 cpus: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 node 0 size: 63678 MB node 0 free: 59542 MB node 1 cpus: node 1 size: 16122 MB node 1 free: 15627 MB node distances: node 0 1 0: 10 50 1: 50 10 CPU list for CXL memory will be empty. The cpu-cxl node distance is greater than cpu-to-cpu distances. Node 1 has the CXL memory in this case. CXL memory can also be identified using ACPI SRAT table and memory maps. Feature description is available in the specification, "AMD64 Technology Platform Quality of Service Extensions, Revision: 1.03 Publication # 56375 Revision: 1.03 Issue Date: February 2022". Link: https://www.amd.com/en/support/tech-docs/amd64-technology-platform-qu= ality-service-extensions Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/scattered.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index ef4775c6db01..349852b9daa4 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -304,6 +304,7 @@ #define X86_FEATURE_UNRET (11*32+15) /* "" AMD BTB untrain return */ #define X86_FEATURE_USE_IBPB_FW (11*32+16) /* "" Use IBPB during runtime = firmware calls */ #define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM exit w= hen EIBRS is enabled */ +#define X86_FEATURE_SMBA (11*32+18) /* Slow Memory Bandwidth Allocation */ =20 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c index fd44b54c90d5..885ecf46abb2 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -44,6 +44,7 @@ static const struct cpuid_bit cpuid_bits[] =3D { { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 }, { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, + { X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 }, { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, { 0, 0, 0, 0, 0 } }; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT078.mail.protection.outlook.com (10.13.176.251) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5654.14 via Frontend Transport; Tue, 27 Sep 2022 20:25:42 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Tue, 27 Sep 2022 15:25:40 -0500 Subject: [PATCH v5 02/12] x86/resctrl: Add a new resource type RDT_RESOURCE_SMBA From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Tue, 27 Sep 2022 15:25:40 -0500 Message-ID: <166431034040.373387.6952407781810455057.stgit@bmoger-ubuntu> In-Reply-To: <166431016617.373387.1968875281081252467.stgit@bmoger-ubuntu> References: <166431016617.373387.1968875281081252467.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Sep 2022 20:25:42.8446 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5617b753-dc59-47dc-7679-08daa0c67391 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT078.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4122 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a new resource type RDT_RESOURCE_SMBA to handle the QoS enforcement policies on the external slow memory. Signed-off-by: Babu Moger Reviewed-by: Ingo Molnar --- arch/x86/kernel/cpu/resctrl/core.c | 12 ++++++++++++ arch/x86/kernel/cpu/resctrl/internal.h | 1 + 2 files changed, 13 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index c2657754672e..a7e9aabff8c8 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -100,6 +100,18 @@ struct rdt_hw_resource rdt_resources_all[] =3D { .fflags =3D RFTYPE_RES_MB, }, }, + [RDT_RESOURCE_SMBA] =3D + { + .r_resctrl =3D { + .rid =3D RDT_RESOURCE_SMBA, + .name =3D "SMBA", + .cache_level =3D 3, + .domains =3D domain_init(RDT_RESOURCE_SMBA), + .parse_ctrlval =3D parse_bw, + .format_str =3D "%d=3D%*u", + .fflags =3D RFTYPE_RES_MB, + }, + }, }; =20 /* diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 1d647188a43b..24a1dfeb6cb2 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -418,6 +418,7 @@ enum resctrl_res_level { RDT_RESOURCE_L3, RDT_RESOURCE_L2, RDT_RESOURCE_MBA, + RDT_RESOURCE_SMBA, =20 /* Must be the last */ RDT_NUM_RESOURCES, From nobody Mon Apr 6 11:52:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2810C07E9D for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT070.mail.protection.outlook.com (10.13.177.50) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5676.17 via Frontend Transport; Tue, 27 Sep 2022 20:25:50 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Tue, 27 Sep 2022 15:25:48 -0500 Subject: [PATCH v5 03/12] x86/cpufeatures: Add Bandwidth Monitoring Event Configuration feature flag From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Tue, 27 Sep 2022 15:25:47 -0500 Message-ID: <166431034744.373387.16358042395909100441.stgit@bmoger-ubuntu> In-Reply-To: <166431016617.373387.1968875281081252467.stgit@bmoger-ubuntu> References: <166431016617.373387.1968875281081252467.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Sep 2022 20:25:50.1300 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 05e592c7-dbcc-48bf-1f23-08daa0c677e9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT070.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5340 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Newer AMD processors support the new feature Bandwidth Monitoring Event Configuration (BMEC). The feature support is identified via CPUID Fn8000_0020_EBX_x0 (ECX=3D0). Bits Field Name Description 3 EVT_CFG Bandwidth Monitoring Event Configuration (BMEC) Currently, the bandwidth monitoring events mbm_total_bytes and mbm_local_bytes are set to count all the total and local reads/writes respectively. With the introduction of slow memory, the two counters are not enough to count all the different types of memory events. With the feature BMEC, the users have the option to configure mbm_total_bytes and mbm_local_bytes to count the specific type of events. Each BMEC event has a configuration MSR, QOS_EVT_CFG (0xc000_0400h + EventID) which contains one field for each Bandwidth Type that can be used to configure the bandwidth event to track any combination of supported bandwidth types. The event will count requests from every Bandwidth Type bit that is set in the corresponding configuration register. Following are the types of events supported: =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Bits Description =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D 6 Dirty Victims from the QOS domain to all types of memory 5 Reads to slow memory in the non-local NUMA domain 4 Reads to slow memory in the local NUMA domain 3 Non-temporal writes to non-local NUMA domain 2 Non-temporal writes to local NUMA domain 1 Reads to memory in the non-local NUMA domain 0 Reads to memory in the local NUMA domain =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D By default, the mbm_total_bytes configuration is set to 0x7F to count all the event types and the mbm_local_bytes configuration is set to 0x15 to count all the local memory events. Feature description is available in the specification, "AMD64 Technology Platform Quality of Service Extensions, Revision: 1.03 Publication Link: https://www.amd.com/en/support/tech-docs/amd64-technology-platform-qu= ality-service-extensions Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/cpuid-deps.c | 1 + arch/x86/kernel/cpu/scattered.c | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 349852b9daa4..896226c5470b 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -305,6 +305,7 @@ #define X86_FEATURE_USE_IBPB_FW (11*32+16) /* "" Use IBPB during runtime = firmware calls */ #define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM exit w= hen EIBRS is enabled */ #define X86_FEATURE_SMBA (11*32+18) /* Slow Memory Bandwidth Allocation */ +#define X86_FEATURE_BMEC (11*32+19) /* AMD Bandwidth Monitoring Event Con= figuration (BMEC) */ =20 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-d= eps.c index c881bcafba7d..4555f9596ccf 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -68,6 +68,7 @@ static const struct cpuid_dep cpuid_deps[] =3D { { X86_FEATURE_CQM_OCCUP_LLC, X86_FEATURE_CQM_LLC }, { X86_FEATURE_CQM_MBM_TOTAL, X86_FEATURE_CQM_LLC }, { X86_FEATURE_CQM_MBM_LOCAL, X86_FEATURE_CQM_LLC }, + { X86_FEATURE_BMEC, X86_FEATURE_CQM_LLC }, { X86_FEATURE_AVX512_BF16, X86_FEATURE_AVX512VL }, { X86_FEATURE_AVX512_FP16, X86_FEATURE_AVX512BW }, { X86_FEATURE_ENQCMD, X86_FEATURE_XSAVES }, diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c index 885ecf46abb2..7981df0b910e 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -45,6 +45,7 @@ static const struct cpuid_bit cpuid_bits[] =3D { { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, { X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 }, + { X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 }, { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, { 0, 0, 0, 0, 0 } }; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT058.mail.protection.outlook.com (10.13.177.58) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5676.17 via Frontend Transport; Tue, 27 Sep 2022 20:26:02 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Tue, 27 Sep 2022 15:26:00 -0500 Subject: [PATCH v5 04/12] x86/resctrl: Include new features in command line options From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Tue, 27 Sep 2022 15:25:54 -0500 Message-ID: <166431035471.373387.5266268593915885892.stgit@bmoger-ubuntu> In-Reply-To: <166431016617.373387.1968875281081252467.stgit@bmoger-ubuntu> References: <166431016617.373387.1968875281081252467.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Sep 2022 20:26:02.1932 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d1a567a9-c501-4fb3-d0a3-08daa0c67f19 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT058.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5270 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the command line options to disable the new features. smba : Slow Memory Bandwidth Allocation bmec : Bandwidth Monitor Event Configuration. Signed-off-by: Babu Moger --- Documentation/admin-guide/kernel-parameters.txt | 2 +- arch/x86/kernel/cpu/resctrl/core.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index 426fa892d311..71b397cc776c 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -5169,7 +5169,7 @@ rdt=3D [HW,X86,RDT] Turn on/off individual RDT features. List is: cmt, mbmtotal, mbmlocal, l3cat, l3cdp, l2cat, l2cdp, - mba. + mba, smba, bmec. E.g. to turn on cmt and turn off mba use: rdt=3Dcmt,!mba =20 diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index a7e9aabff8c8..53fbc3acad81 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -700,6 +700,8 @@ enum { RDT_FLAG_L2_CAT, RDT_FLAG_L2_CDP, RDT_FLAG_MBA, + RDT_FLAG_SMBA, + RDT_FLAG_BMEC, }; =20 #define RDT_OPT(idx, n, f) \ @@ -723,6 +725,8 @@ static struct rdt_options rdt_options[] __initdata =3D= { RDT_OPT(RDT_FLAG_L2_CAT, "l2cat", X86_FEATURE_CAT_L2), RDT_OPT(RDT_FLAG_L2_CDP, "l2cdp", X86_FEATURE_CDP_L2), RDT_OPT(RDT_FLAG_MBA, "mba", X86_FEATURE_MBA), + RDT_OPT(RDT_FLAG_SMBA, "smba", X86_FEATURE_SMBA), + RDT_OPT(RDT_FLAG_BMEC, "bmec", X86_FEATURE_BMEC), }; #define NUM_RDT_OPTIONS ARRAY_SIZE(rdt_options) =20 From nobody Mon Apr 6 11:52:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A292C54EE9 for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Sep 2022 20:26:09.1175 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 661f3d01-db7a-4e57-6309-08daa0c6833a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT097.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4142 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The QoS slow memory configuration details are available via CPUID_Fn80000020_EDX_x02. Detect the available details and initialize the rest to defaults. Signed-off-by: Babu Moger --- arch/x86/kernel/cpu/resctrl/core.c | 29 +++++++++++++++++++++++++= ++-- arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 2 +- arch/x86/kernel/cpu/resctrl/internal.h | 1 + arch/x86/kernel/cpu/resctrl/rdtgroup.c | 8 +++++--- 4 files changed, 34 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 53fbc3acad81..56c96607259c 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -227,9 +227,15 @@ static bool __rdt_get_mem_config_amd(struct rdt_resour= ce *r) struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r); union cpuid_0x10_3_eax eax; union cpuid_0x10_x_edx edx; - u32 ebx, ecx; + u32 ebx, ecx, subleaf; + + /* + * Query CPUID_Fn80000020_EDX_x01 for MBA and + * CPUID_Fn80000020_EDX_x02 for SMBA + */ + subleaf =3D (r->rid =3D=3D RDT_RESOURCE_SMBA) ? 2 : 1; =20 - cpuid_count(0x80000020, 1, &eax.full, &ebx, &ecx, &edx.full); + cpuid_count(0x80000020, subleaf, &eax.full, &ebx, &ecx, &edx.full); hw_res->num_closid =3D edx.split.cos_max + 1; r->default_ctrl =3D MAX_MBA_BW_AMD; =20 @@ -791,6 +797,19 @@ static __init bool get_mem_config(void) return false; } =20 +static __init bool get_slow_mem_config(void) +{ + struct rdt_hw_resource *hw_res =3D &rdt_resources_all[RDT_RESOURCE_SMBA]; + + if (!rdt_cpu_has(X86_FEATURE_SMBA)) + return false; + + if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD) + return __rdt_get_mem_config_amd(&hw_res->r_resctrl); + + return false; +} + static __init bool get_rdt_alloc_resources(void) { struct rdt_resource *r; @@ -821,6 +840,9 @@ static __init bool get_rdt_alloc_resources(void) if (get_mem_config()) ret =3D true; =20 + if (get_slow_mem_config()) + ret =3D true; + return ret; } =20 @@ -910,6 +932,9 @@ static __init void rdt_init_res_defs_amd(void) } else if (r->rid =3D=3D RDT_RESOURCE_MBA) { hw_res->msr_base =3D MSR_IA32_MBA_BW_BASE; hw_res->msr_update =3D mba_wrmsr_amd; + } else if (r->rid =3D=3D RDT_RESOURCE_SMBA) { + hw_res->msr_base =3D MSR_IA32_SMBA_BW_BASE; + hw_res->msr_update =3D mba_wrmsr_amd; } } } diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cp= u/resctrl/ctrlmondata.c index 7f38c8bd8429..480600b8e4cf 100644 --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c @@ -202,7 +202,7 @@ static int parse_line(char *line, struct resctrl_schema= *s, unsigned long dom_id; =20 if (rdtgrp->mode =3D=3D RDT_MODE_PSEUDO_LOCKSETUP && - r->rid =3D=3D RDT_RESOURCE_MBA) { + (r->rid =3D=3D RDT_RESOURCE_MBA || r->rid =3D=3D RDT_RESOURCE_SMBA)) { rdt_last_cmd_puts("Cannot pseudo-lock MBA resource\n"); return -EINVAL; } diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 24a1dfeb6cb2..c049a274383c 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -14,6 +14,7 @@ #define MSR_IA32_L2_CBM_BASE 0xd10 #define MSR_IA32_MBA_THRTL_BASE 0xd50 #define MSR_IA32_MBA_BW_BASE 0xc0000200 +#define MSR_IA32_SMBA_BW_BASE 0xc0000280 =20 #define MSR_IA32_QM_CTR 0x0c8e #define MSR_IA32_QM_EVTSEL 0x0c8d diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index f276aff521e8..04b519bca50d 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1218,7 +1218,7 @@ static bool rdtgroup_mode_test_exclusive(struct rdtgr= oup *rdtgrp) =20 list_for_each_entry(s, &resctrl_schema_all, list) { r =3D s->res; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT056.mail.protection.outlook.com (10.13.173.99) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5676.17 via Frontend Transport; Tue, 27 Sep 2022 20:26:16 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Tue, 27 Sep 2022 15:26:14 -0500 Subject: [PATCH v5 06/12] x86/resctrl: Introduce data structure to support monitor configuration From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Tue, 27 Sep 2022 15:26:13 -0500 Message-ID: <166431037370.373387.14792678048042598706.stgit@bmoger-ubuntu> In-Reply-To: <166431016617.373387.1968875281081252467.stgit@bmoger-ubuntu> References: <166431016617.373387.1968875281081252467.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Sep 2022 20:26:16.2680 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bca90984-3d85-4183-d775-08daa0c6877f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT056.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4864 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add couple of fields in mon_evt to support Bandwidth Monitoring Event Configuratio (BMEC) and also update the "mon_features". The sysfs file "mon_features" will display the monitor configuration if supported. Before the change. $cat /sys/fs/resctrl/info/L3_MON/mon_features llc_occupancy mbm_total_bytes mbm_local_bytes After the change if BMEC is supported. $cat /sys/fs/resctrl/info/L3_MON/mon_features llc_occupancy mbm_total_bytes mbm_total_config mbm_local_bytes mbm_local_config Signed-off-by: Babu Moger --- arch/x86/kernel/cpu/resctrl/core.c | 3 ++- arch/x86/kernel/cpu/resctrl/internal.h | 6 +++++- arch/x86/kernel/cpu/resctrl/monitor.c | 9 ++++++++- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 5 ++++- 4 files changed, 19 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 56c96607259c..513e6a00f58e 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -849,6 +849,7 @@ static __init bool get_rdt_alloc_resources(void) static __init bool get_rdt_mon_resources(void) { struct rdt_resource *r =3D &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl; + bool mon_configurable =3D rdt_cpu_has(X86_FEATURE_BMEC); =20 if (rdt_cpu_has(X86_FEATURE_CQM_OCCUP_LLC)) rdt_mon_features |=3D (1 << QOS_L3_OCCUP_EVENT_ID); @@ -860,7 +861,7 @@ static __init bool get_rdt_mon_resources(void) if (!rdt_mon_features) return false; =20 - return !rdt_get_mon_l3_config(r); + return !rdt_get_mon_l3_config(r, mon_configurable); } =20 static __init void __check_quirks_intel(void) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index c049a274383c..4d03f443b353 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -72,11 +72,15 @@ DECLARE_STATIC_KEY_FALSE(rdt_mon_enable_key); * struct mon_evt - Entry in the event list of a resource * @evtid: event id * @name: name of the event + * @configurable: true if the event is configurable + * @config_name: sysfs file name of the event if configurable * @list: entry in &rdt_resource->evt_list */ struct mon_evt { u32 evtid; char *name; + bool configurable; + char *config_name; struct list_head list; }; =20 @@ -529,7 +533,7 @@ int closids_supported(void); void closid_free(int closid); int alloc_rmid(void); void free_rmid(u32 rmid); -int rdt_get_mon_l3_config(struct rdt_resource *r); +int rdt_get_mon_l3_config(struct rdt_resource *r, bool configurable); void mon_event_count(void *info); int rdtgroup_mondata_show(struct seq_file *m, void *arg); void rmdir_mondata_subdir_allrdtgrp(struct rdt_resource *r, diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index eaf25a234ff5..dc97aa7a3b3d 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -656,11 +656,13 @@ static struct mon_evt llc_occupancy_event =3D { static struct mon_evt mbm_total_event =3D { .name =3D "mbm_total_bytes", .evtid =3D QOS_L3_MBM_TOTAL_EVENT_ID, + .config_name =3D "mbm_total_config", }; =20 static struct mon_evt mbm_local_event =3D { .name =3D "mbm_local_bytes", .evtid =3D QOS_L3_MBM_LOCAL_EVENT_ID, + .config_name =3D "mbm_local_config", }; =20 /* @@ -682,7 +684,7 @@ static void l3_mon_evt_init(struct rdt_resource *r) list_add_tail(&mbm_local_event.list, &r->evt_list); } =20 -int rdt_get_mon_l3_config(struct rdt_resource *r) +int rdt_get_mon_l3_config(struct rdt_resource *r, bool configurable) { unsigned int mbm_offset =3D boot_cpu_data.x86_cache_mbm_width_offset; struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r); @@ -714,6 +716,11 @@ int rdt_get_mon_l3_config(struct rdt_resource *r) if (ret) return ret; =20 + if (configurable) { + mbm_total_event.configurable =3D true; + mbm_local_event.configurable =3D true; + } + l3_mon_evt_init(r); =20 r->mon_capable =3D true; diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 04b519bca50d..834a55d78e3f 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1001,8 +1001,11 @@ static int rdt_mon_features_show(struct kernfs_open_= file *of, struct rdt_resource *r =3D of->kn->parent->priv; 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Tue, 27 Sep 2022 20:26:23 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT062.mail.protection.outlook.com (10.13.173.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5654.14 via Frontend Transport; Tue, 27 Sep 2022 20:26:23 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Tue, 27 Sep 2022 15:26:21 -0500 Subject: [PATCH v5 07/12] x86/resctrl: Add sysfs interface to read mbm_total_bytes event configuration From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Tue, 27 Sep 2022 15:26:20 -0500 Message-ID: <166431038074.373387.12300700929220707129.stgit@bmoger-ubuntu> In-Reply-To: <166431016617.373387.1968875281081252467.stgit@bmoger-ubuntu> References: <166431016617.373387.1968875281081252467.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Sep 2022 20:26:23.1950 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0978407b-48a7-4ad7-d4ba-08daa0c68ba0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT062.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5318 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The current event configuration can be viewed by the user by reading the configuration file /sys/fs/resctrl/info/L3_MON/mbm_total_config. Following are the types of events supported: =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Bits Description =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D 6 Dirty Victims from the QOS domain to all types of memory 5 Reads to slow memory in the non-local NUMA domain 4 Reads to slow memory in the local NUMA domain 3 Non-temporal writes to non-local NUMA domain 2 Non-temporal writes to local NUMA domain 1 Reads to memory in the non-local NUMA domain 0 Reads to memory in the local NUMA domain =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D By default, the mbm_total_bytes configuration is set to 0x7f to count all the event types. The event configuration settings are domain specific. Changing the configuration on one CPU in a domain would affect the whole domain. For example: $cat /sys/fs/resctrl/info/L3_MON/mbm_total_config 0:0x7f;1:0x7f;2:0x7f;3:0x7f In this case, the event mbm_total_bytes is currently configured with 0x7f on domains 0 to 3. Signed-off-by: Babu Moger --- arch/x86/kernel/cpu/resctrl/core.c | 3 + arch/x86/kernel/cpu/resctrl/internal.h | 2 + arch/x86/kernel/cpu/resctrl/rdtgroup.c | 76 ++++++++++++++++++++++++++++= ++++ 3 files changed, 81 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 513e6a00f58e..b3bb8badbaaa 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -861,6 +861,9 @@ static __init bool get_rdt_mon_resources(void) if (!rdt_mon_features) return false; =20 + if (mon_configurable) + mbm_config_rftype_init(); + return !rdt_get_mon_l3_config(r, mon_configurable); } =20 diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 4d03f443b353..44d3f18dfd69 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -15,6 +15,7 @@ #define MSR_IA32_MBA_THRTL_BASE 0xd50 #define MSR_IA32_MBA_BW_BASE 0xc0000200 #define MSR_IA32_SMBA_BW_BASE 0xc0000280 +#define MSR_IA32_EVT_CFG_BASE 0xc0000400 =20 #define MSR_IA32_QM_CTR 0x0c8e #define MSR_IA32_QM_EVTSEL 0x0c8d @@ -556,5 +557,6 @@ bool has_busy_rmid(struct rdt_resource *r, struct rdt_d= omain *d); void __check_limbo(struct rdt_domain *d, bool force_free); void rdt_domain_reconfigure_cdp(struct rdt_resource *r); void __init thread_throttle_mode_init(void); +void __init mbm_config_rftype_init(void); =20 #endif /* _ASM_X86_RESCTRL_INTERNAL_H */ diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 834a55d78e3f..b51fae77ba5c 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1420,6 +1420,67 @@ static int rdtgroup_size_show(struct kernfs_open_fil= e *of, return ret; } =20 +struct mon_config_info { + u32 evtid; + u32 mon_config; +}; + +void mon_event_config_read(void *info) +{ + struct mon_config_info *mon_info =3D info; + u32 h, msr_index; + + switch (mon_info->evtid) { + case QOS_L3_MBM_TOTAL_EVENT_ID: + msr_index =3D 0; + break; + case QOS_L3_MBM_LOCAL_EVENT_ID: + msr_index =3D 1; + break; + default: + /* Not expected to come here */ + return; + } + + rdmsr(MSR_IA32_EVT_CFG_BASE + msr_index, mon_info->mon_config, h); +} + +void mondata_config_read(struct rdt_domain *d, struct mon_config_info *mon= _info) +{ + smp_call_function_any(&d->cpu_mask, mon_event_config_read, mon_info, 1); +} + +unsigned int mbm_config_show(struct seq_file *s, struct rdt_resource *r, u= 32 evtid) +{ + struct mon_config_info mon_info =3D {0}; + struct rdt_domain *dom; + bool sep =3D false; + + list_for_each_entry(dom, &r->domains, list) { + if (sep) + seq_puts(s, ";"); + + mon_info.evtid =3D evtid; + mondata_config_read(dom, &mon_info); + + seq_printf(s, "%d:0x%02x", dom->id, mon_info.mon_config); + sep =3D true; + } + seq_puts(s, "\n"); + + return 0; +} + +static int mbm_total_config_show(struct kernfs_open_file *of, + struct seq_file *seq, void *v) +{ + struct rdt_resource *r =3D of->kn->parent->priv; + + mbm_config_show(seq, r, QOS_L3_MBM_TOTAL_EVENT_ID); + + return 0; +} + /* rdtgroup information files for one cache resource. */ static struct rftype res_common_files[] =3D { { @@ -1518,6 +1579,12 @@ static struct rftype res_common_files[] =3D { .seq_show =3D max_threshold_occ_show, .fflags =3D RF_MON_INFO | RFTYPE_RES_CACHE, }, + { + .name =3D "mbm_total_config", + .mode =3D 0644, + .kf_ops =3D &rdtgroup_kf_single_ops, + .seq_show =3D mbm_total_config_show, + }, { .name =3D "cpus", .mode =3D 0644, @@ -1624,6 +1691,15 @@ void __init thread_throttle_mode_init(void) rft->fflags =3D RF_CTRL_INFO | RFTYPE_RES_MB; } =20 +void __init mbm_config_rftype_init(void) +{ + struct rftype *rft; + + rft =3D rdtgroup_get_rftype_by_name("mbm_total_config"); + if (rft) + rft->fflags =3D RF_MON_INFO | RFTYPE_RES_CACHE; +} + /** * rdtgroup_kn_mode_restrict - Restrict user access to named resctrl file * @r: The resource group with which the file is associated. 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT078.mail.protection.outlook.com (10.13.173.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5654.14 via Frontend Transport; Tue, 27 Sep 2022 20:26:35 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Tue, 27 Sep 2022 15:26:33 -0500 Subject: [PATCH v5 08/12] x86/resctrl: Add sysfs interface to read mbm_local_bytes event configuration From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Tue, 27 Sep 2022 15:26:27 -0500 Message-ID: <166431038771.373387.9706240777220251603.stgit@bmoger-ubuntu> In-Reply-To: <166431016617.373387.1968875281081252467.stgit@bmoger-ubuntu> References: <166431016617.373387.1968875281081252467.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT078:EE_|DM4PR12MB6136:EE_ X-MS-Office365-Filtering-Correlation-Id: 93dcea6e-d4cc-454f-cfe1-08daa0c692d2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: n9cSk4lK2Jh6j6dUaYo4lf1jezjvsg1y7n2Ea6KkrArUO0aB4O2TF4C/sZhkg4Y39kBD0HXi6i6/0kgb9zHlmR/uRJ8Vt+sIPHlHptTktRxaFoE9O6ijPcx8awxgEnbXMOZK/oIgYQ9/WJtEquEoocGQp70TXBk0e/uED2jDA42UhK+NCZyowcreyGO0IfKccW0Z1PfaWN72mZfwWKN1glNA8CloZ7u0mzeIzymwqsMpDNeBkfl4QXYCwasu47laNesTbCJAMGyMu9hAahe9g+ZsB0/rKr4pM8ILQmPygBFDidZtyTnP+VY56VOCHEv3qBYchOvpJ2fif37g2+WTBHeUFgYaK2ijnb0NFD8ETmfZhkOqWDCrgVzjUDMGDxNUFLsFdW2azRrCQguKATcVyktmZZ1XPMKJTgfR+DUtqoWMmZqbgquJC/ys1ta5unQ0t7xnJgcm7/05kGZg/z8wlAE5EWlUzvwthN+ktDPSE7B9aYvnV3mSjqnY32O5nkpBZ//PSC9hb+23FINcRpXNwpPSE/biQ//Zun/xlarq1dWejDTiusad/aI2jXhb6JfAPTkofyc+XAVYy3Wtzn/KJnx3bkc3H35JHO92h/r7sPOUT0ce9VFCsy+PmJWEMoSJNAATtNjrhOavgL36lqXGaOHpB+N2tEOy6aoP36tgfJLa9u6UUH1zx4ZezkZo0bqt1IdcAOZd5r2i1TD9pJfo1DJkhwqLREbA4IwMGpAWDqA8atJaKROrpOvm836i1jr5ZoHrANLOyO9hCLXdv1T12mKuCC6QJcHbbkXfzaoOX5NZ3qfk3lhuQTSAeWOTMAdOjAPMEhflh4SAPHdx9cpayQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(7916004)(4636009)(39860400002)(346002)(136003)(376002)(396003)(451199015)(36840700001)(40470700004)(46966006)(33716001)(82310400005)(5660300002)(41300700001)(2906002)(7416002)(44832011)(8936002)(426003)(110136005)(356005)(36860700001)(81166007)(70206006)(4326008)(70586007)(40480700001)(8676002)(478600001)(54906003)(16576012)(103116003)(316002)(47076005)(82740400003)(26005)(16526019)(186003)(336012)(9686003)(86362001)(40460700003)(6666004)(71626007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Sep 2022 20:26:35.2667 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 93dcea6e-d4cc-454f-cfe1-08daa0c692d2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT078.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6136 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The current event configuration can be viewed by the user by reading the configuration file /sys/fs/resctrl/info/L3_MON/mbm_local_config. Following are the types of events supported: =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Bits Description =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D 6 Dirty Victims from the QOS domain to all types of memory 5 Reads to slow memory in the non-local NUMA domain 4 Reads to slow memory in the local NUMA domain 3 Non-temporal writes to non-local NUMA domain 2 Non-temporal writes to local NUMA domain 1 Reads to memory in the non-local NUMA domain 0 Reads to memory in the local NUMA domain =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D By default, the mbm_local_bytes configuration is set to 0x15 to count all the local event types. The event configuration settings are domain specific. Changing the configuration on one CPU in a domain would affect the whole domain. For example: $cat /sys/fs/resctrl/info/L3_MON/mbm_local_config 0:0x15;1:0x15;2:0x15;3:0x15 In this case the event mbm_local_bytes is currently configured with 0x15 on domains 0 to 3. Signed-off-by: Babu Moger --- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index b51fae77ba5c..27bf6ade0dbf 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1481,6 +1481,16 @@ static int mbm_total_config_show(struct kernfs_open_= file *of, return 0; } =20 +static int mbm_local_config_show(struct kernfs_open_file *of, + struct seq_file *seq, void *v) +{ + struct rdt_resource *r =3D of->kn->parent->priv; + + mbm_config_show(seq, r, QOS_L3_MBM_LOCAL_EVENT_ID); + + return 0; +} + /* rdtgroup information files for one cache resource. */ static struct rftype res_common_files[] =3D { { @@ -1585,6 +1595,12 @@ static struct rftype res_common_files[] =3D { .kf_ops =3D &rdtgroup_kf_single_ops, .seq_show =3D mbm_total_config_show, }, + { + .name =3D "mbm_local_config", + .mode =3D 0644, + .kf_ops =3D &rdtgroup_kf_single_ops, + .seq_show =3D mbm_local_config_show, + }, { .name =3D "cpus", .mode =3D 0644, @@ -1698,6 +1714,10 @@ void __init mbm_config_rftype_init(void) rft =3D rdtgroup_get_rftype_by_name("mbm_total_config"); if (rft) rft->fflags =3D RF_MON_INFO | RFTYPE_RES_CACHE; + + rft =3D rdtgroup_get_rftype_by_name("mbm_local_config"); + if (rft) + rft->fflags =3D RF_MON_INFO | RFTYPE_RES_CACHE; } =20 /** From nobody Mon Apr 6 11:52:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA354C07E9D for ; Tue, 27 Sep 2022 20:27:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233135AbiI0U1r (ORCPT ); Tue, 27 Sep 2022 16:27:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39950 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232959AbiI0U1I (ORCPT ); Tue, 27 Sep 2022 16:27:08 -0400 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2075.outbound.protection.outlook.com [40.107.220.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 822F8A3D01; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Sep 2022 20:26:42.1277 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e313eb0a-448c-4d0c-1b32-08daa0c696ec X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT114.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6595 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The current event configuration can be changed by the user by writing to the configuration file /sys/fs/resctrl/info/L3_MON/mbm_total_config. The event configuration settings are domain specific. Changing the configuration on one CPU in a domain would affect the whole domain. Following are the types of events supported: =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Bits Description =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D 6 Dirty Victims from the QOS domain to all types of memory 5 Reads to slow memory in the non-local NUMA domain 4 Reads to slow memory in the local NUMA domain 3 Non-temporal writes to non-local NUMA domain 2 Non-temporal writes to local NUMA domain 1 Reads to memory in the non-local NUMA domain 0 Reads to memory in the local NUMA domain =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D For example: To change the mbm_total_bytes to count all the reads on domain 0, run the command. $echo 0:0x33 > /sys/fs/resctrl/info/L3_MON/mbm_total_config To change the mbm_total_bytes to count all the slow memory reads on domain 1, run the command. $echo 1:0x30 > /sys/fs/resctrl/info/L3_MON/mbm_total_config Signed-off-by: Babu Moger --- arch/x86/kernel/cpu/resctrl/internal.h | 23 +++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 139 ++++++++++++++++++++++++++++= ++++ 2 files changed, 162 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 44d3f18dfd69..d19ade3b5ef3 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -51,6 +51,29 @@ */ #define MBM_CNTR_WIDTH_OFFSET_MAX (62 - MBM_CNTR_WIDTH_BASE) =20 +/* Reads to Local DRAM Memory */ +#define READS_TO_LOCAL_MEM BIT(0) + +/* Reads to Remote DRAM Memory */ +#define READS_TO_REMOTE_MEM BIT(1) + +/* Non-Temporal Writes to Local Memory */ +#define NON_TEMP_WRITE_TO_LOCAL_MEM BIT(2) + +/* Non-Temporal Writes to Remote Memory */ +#define NON_TEMP_WRITE_TO_REMOTE_MEM BIT(3) + +/* Reads to Local Memory the system identifies as "Slow Memory" */ +#define READS_TO_LOCAL_S_MEM BIT(4) + +/* Reads to Remote Memory the system identifies as "Slow Memory" */ +#define READS_TO_REMOTE_S_MEM BIT(5) + +/* Dirty Victims to All Types of Memory */ +#define DIRTY_VICTIMS_TO_ALL_MEM BIT(6) + +/* Max event bits supported */ +#define MAX_EVT_CONFIG_BITS GENMASK(6, 0) =20 struct rdt_fs_context { struct kernfs_fs_context kfc; diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 27bf6ade0dbf..c1d43d03846a 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1491,6 +1491,144 @@ static int mbm_local_config_show(struct kernfs_open= _file *of, return 0; } =20 +void mon_event_config_write(void *info) +{ + struct mon_config_info *mon_info =3D info; + u32 msr_index; + + switch (mon_info->evtid) { + case QOS_L3_MBM_TOTAL_EVENT_ID: + msr_index =3D 0; + break; + case QOS_L3_MBM_LOCAL_EVENT_ID: + msr_index =3D 1; + break; + default: + /* Not expected to come here */ + return; + } + + wrmsr(MSR_IA32_EVT_CFG_BASE + msr_index, mon_info->mon_config, 0); +} + +int mbm_config_write(struct rdt_resource *r, struct rdt_domain *d, + u32 evtid, u32 val) +{ + struct mon_config_info mon_info =3D {0}; + cpumask_var_t cpu_mask; + int ret =3D 0, cpu; + + rdt_last_cmd_clear(); + + /* mon_config cannot be more than the supported set of events */ + if (val > MAX_EVT_CONFIG_BITS) { + rdt_last_cmd_puts("Invalid event configuration\n"); + return -EINVAL; + } + + cpus_read_lock(); + + if (!zalloc_cpumask_var(&cpu_mask, GFP_KERNEL)) { + rdt_last_cmd_puts("cpu_mask allocation failed\n"); + ret =3D -ENOMEM; + goto e_unlock; + } + + /* + * Read the current config value first. If both are same then + * we dont need to write it again. + */ + mon_info.evtid =3D evtid; + mondata_config_read(d, &mon_info); + if (mon_info.mon_config =3D=3D val) + goto e_cpumask; + + mon_info.mon_config =3D val; + + /* Pick all the CPUs in the domain instance */ + for_each_cpu(cpu, &d->cpu_mask) + cpumask_set_cpu(cpu, cpu_mask); + + /* Update MSR_IA32_EVT_CFG_BASE MSR on all the CPUs in cpu_mask */ + on_each_cpu_mask(cpu_mask, mon_event_config_write, &mon_info, 1); + + /* + * When an Event Configuration is changed, the bandwidth counters + * for all RMIDs and Events will be cleared by the hardware. The + * hardware also sets MSR_IA32_QM_CTR.Unavailable (bit 62) for + * every RMID on the next read to any event for every RMID. + * Subsequent reads will have MSR_IA32_QM_CTR.Unavailable (bit 62) + * cleared while it is tracked by the hardware. Clear the + * mbm_local and mbm_total counts for all the RMIDs. + */ + memset(d->mbm_local, 0, sizeof(struct mbm_state) * r->num_rmid); + memset(d->mbm_total, 0, sizeof(struct mbm_state) * r->num_rmid); + +e_cpumask: + free_cpumask_var(cpu_mask); + +e_unlock: + cpus_read_unlock(); + + return ret; +} + +unsigned int mon_config_parse(struct rdt_resource *r, char *tok, u32 evtid) +{ + char *dom_str =3D NULL, *id_str; + struct rdt_domain *d; + unsigned long dom_id, val; + int ret =3D 0; + +next: + if (!tok || tok[0] =3D=3D '\0') + return 0; + + /* Start processing the strings for each domain */ + dom_str =3D strim(strsep(&tok, ";")); + id_str =3D strsep(&dom_str, "=3D"); + + if (!dom_str || kstrtoul(id_str, 10, &dom_id)) { + rdt_last_cmd_puts("Missing '=3D' or non-numeric domain id\n"); + return -EINVAL; + } + + if (!dom_str || kstrtoul(dom_str, 16, &val)) { + rdt_last_cmd_puts("Missing '=3D' or non-numeric event configuration valu= e\n"); + return -EINVAL; + } + + list_for_each_entry(d, &r->domains, list) { + if (d->id =3D=3D dom_id) { + ret =3D mbm_config_write(r, d, evtid, val); + if (ret) + return -EINVAL; + goto next; + } + } + + return -EINVAL; +} + +static ssize_t mbm_total_config_write(struct kernfs_open_file *of, + char *buf, size_t nbytes, loff_t off) +{ + struct rdt_resource *r =3D of->kn->parent->priv; + int ret; + + /* Valid input requires a trailing newline */ + if (nbytes =3D=3D 0 || buf[nbytes - 1] !=3D '\n') + return -EINVAL; + + rdt_last_cmd_clear(); + + buf[nbytes - 1] =3D '\0'; + + ret =3D mon_config_parse(r, buf, QOS_L3_MBM_TOTAL_EVENT_ID); + + return ret ?: nbytes; +} + /* rdtgroup information files for one cache resource. */ static struct rftype res_common_files[] =3D { { @@ -1594,6 +1732,7 @@ static struct rftype res_common_files[] =3D { .mode =3D 0644, .kf_ops =3D &rdtgroup_kf_single_ops, .seq_show =3D mbm_total_config_show, + .write =3D mbm_total_config_write, }, { .name =3D "mbm_local_config", From nobody Mon Apr 6 11:52:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49879C54EE9 for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT108.mail.protection.outlook.com (10.13.172.95) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5676.17 via Frontend Transport; Tue, 27 Sep 2022 20:26:49 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Tue, 27 Sep 2022 15:26:47 -0500 Subject: [PATCH v5 10/12] x86/resctrl: Add sysfs interface to write mbm_local_bytes event configuration From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Tue, 27 Sep 2022 15:26:46 -0500 Message-ID: <166431040665.373387.16611336653801046307.stgit@bmoger-ubuntu> In-Reply-To: <166431016617.373387.1968875281081252467.stgit@bmoger-ubuntu> References: <166431016617.373387.1968875281081252467.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Sep 2022 20:26:49.2190 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3006a763-18cd-4f94-263c-08daa0c69b26 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT108.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7366 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The current event configuration can be changed by the user by writing to the configuration file /sys/fs/resctrl/info/L3_MON/mbm_local_config. The event configuration settings are domain specific. Changing the configuration on one CPU in a domain would affect the whole domain. Following are the types of events supported: =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Bits Description =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D 6 Dirty Victims from the QOS domain to all types of memory 5 Reads to slow memory in the non-local NUMA domain 4 Reads to slow memory in the local NUMA domain 3 Non-temporal writes to non-local NUMA domain 2 Non-temporal writes to local NUMA domain 1 Reads to memory in the non-local NUMA domain 0 Reads to memory in the local NUMA domain =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D For example: To change the mbm_local_bytes to count all the reads on domain 0, run the command. $echo 0:0x33 > /sys/fs/resctrl/info/L3_MON/mbm_local_config To change the mbm_local_bytes to count all the slow memory reads on domain 1, run the command. $echo 1:0x30 > /sys/fs/resctrl/info/L3_MON/mbm_local_config Signed-off-by: Babu Moger --- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index c1d43d03846a..87f3f8018c92 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1629,6 +1629,26 @@ static ssize_t mbm_total_config_write(struct kernfs_= open_file *of, return ret ?: nbytes; } =20 +static ssize_t mbm_local_config_write(struct kernfs_open_file *of, + char *buf, size_t nbytes, + loff_t off) +{ + struct rdt_resource *r =3D of->kn->parent->priv; + int ret; + + /* Valid input requires a trailing newline */ + if (nbytes =3D=3D 0 || buf[nbytes - 1] !=3D '\n') + return -EINVAL; + + rdt_last_cmd_clear(); + + buf[nbytes - 1] =3D '\0'; + + ret =3D mon_config_parse(r, buf, QOS_L3_MBM_LOCAL_EVENT_ID); + + return ret ?: nbytes; +} + /* rdtgroup information files for one cache resource. */ static struct rftype res_common_files[] =3D { { @@ -1739,6 +1759,7 @@ static struct rftype res_common_files[] =3D { .mode =3D 0644, .kf_ops =3D &rdtgroup_kf_single_ops, .seq_show =3D mbm_local_config_show, + .write =3D mbm_local_config_write, }, { .name =3D "cpus", From nobody Mon Apr 6 11:52:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BC42C07E9D for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT027.mail.protection.outlook.com (10.13.172.205) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5676.17 via Frontend Transport; Tue, 27 Sep 2022 20:26:56 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Tue, 27 Sep 2022 15:26:54 -0500 Subject: [PATCH v5 11/12] x86/resctrl: Replace smp_call_function_many() with on_each_cpu_mask() From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Tue, 27 Sep 2022 15:26:53 -0500 Message-ID: <166431041367.373387.16343892218388937640.stgit@bmoger-ubuntu> In-Reply-To: <166431016617.373387.1968875281081252467.stgit@bmoger-ubuntu> References: <166431016617.373387.1968875281081252467.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Sep 2022 20:26:56.6354 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e1b716f3-4348-4f14-cfbd-08daa0c69f91 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT027.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6094 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The call on_each_cpu_mask() can run the function on each CPU specified by cpumask, which may include the local processor. So, replace the call smp_call_function_man()y with on_each_cpu_mask() to simplify the code. Signed-off-by: Babu Moger --- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 29 ++++++++--------------------- 1 file changed, 8 insertions(+), 21 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 87f3f8018c92..532bb0025054 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -325,12 +325,7 @@ static void update_cpu_closid_rmid(void *info) static void update_closid_rmid(const struct cpumask *cpu_mask, struct rdtgroup *r) { - int cpu =3D get_cpu(); - - if (cpumask_test_cpu(cpu, cpu_mask)) - update_cpu_closid_rmid(r); - smp_call_function_many(cpu_mask, update_cpu_closid_rmid, r, 1); - put_cpu(); + on_each_cpu_mask(cpu_mask, update_cpu_closid_rmid, r, 1); } =20 static int cpus_mon_write(struct rdtgroup *rdtgrp, cpumask_var_t newmask, @@ -2121,13 +2116,9 @@ static int set_cache_qos_cfg(int level, bool enable) /* Pick one CPU from each domain instance to update MSR */ cpumask_set_cpu(cpumask_any(&d->cpu_mask), cpu_mask); } - cpu =3D get_cpu(); - /* Update QOS_CFG MSR on this cpu if it's in cpu_mask. */ - if (cpumask_test_cpu(cpu, cpu_mask)) - update(&enable); - /* Update QOS_CFG MSR on all other cpus in cpu_mask. */ - smp_call_function_many(cpu_mask, update, &enable, 1); - put_cpu(); + + /* Update QOS_CFG MSR on all the CPUs in cpu_mask */ + on_each_cpu_mask(cpu_mask, update, &enable, 1); =20 free_cpumask_var(cpu_mask); =20 @@ -2569,7 +2560,7 @@ static int reset_all_ctrls(struct rdt_resource *r) struct msr_param msr_param; cpumask_var_t cpu_mask; struct rdt_domain *d; - int i, cpu; + int i; =20 if (!zalloc_cpumask_var(&cpu_mask, GFP_KERNEL)) return -ENOMEM; @@ -2590,13 +2581,9 @@ static int reset_all_ctrls(struct rdt_resource *r) for (i =3D 0; i < hw_res->num_closid; i++) hw_dom->ctrl_val[i] =3D r->default_ctrl; } - cpu =3D get_cpu(); - /* Update CBM on this cpu if it's in cpu_mask. */ - if (cpumask_test_cpu(cpu, cpu_mask)) - rdt_ctrl_update(&msr_param); - /* Update CBM on all other cpus in cpu_mask. */ - smp_call_function_many(cpu_mask, rdt_ctrl_update, &msr_param, 1); - put_cpu(); + + /* Update CBM on all the CPUs in cpu_mask */ + on_each_cpu_mask(cpu_mask, rdt_ctrl_update, &msr_param, 1); =20 free_cpumask_var(cpu_mask); =20 From nobody Mon Apr 6 11:52:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA06BC54EE9 for ; Tue, 27 Sep 2022 20:28:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233109AbiI0U2W (ORCPT ); Tue, 27 Sep 2022 16:28:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42018 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233194AbiI0U1m (ORCPT ); Tue, 27 Sep 2022 16:27:42 -0400 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2054.outbound.protection.outlook.com [40.107.220.54]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 65EBFAD9B9; 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Tue, 27 Sep 2022 20:27:03 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT025.mail.protection.outlook.com (10.13.172.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5676.17 via Frontend Transport; Tue, 27 Sep 2022 20:27:03 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Tue, 27 Sep 2022 15:27:01 -0500 Subject: [PATCH v5 12/12] Documentation/x86: Update resctrl_ui.rst for new features From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Tue, 27 Sep 2022 15:27:00 -0500 Message-ID: <166431042060.373387.8454967155095795574.stgit@bmoger-ubuntu> In-Reply-To: <166431016617.373387.1968875281081252467.stgit@bmoger-ubuntu> References: <166431016617.373387.1968875281081252467.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Sep 2022 20:27:03.2018 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a0ff3670-9b32-436a-c45d-08daa0c6a37b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT025.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB6014 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Update the documentation for the new features: 1. Slow Memory Bandwidth allocation (SMBA). With this feature, the QOS enforcement policies can be applied to the external slow memory connected to the host. QOS enforcement is accomplished by assigning a Class Of Service (COS) to a processor and specifying allocations or limits for that COS for each resource to be allocated. 2. Bandwidth Monitoring Event Configuration (BMEC). The bandwidth monitoring events mbm_total_bytes and mbm_local_bytes are set to count all the total and local reads/writes respectively. With the introduction of slow memory, the two counters are not enough to count all the different types are memory events. With the feature BMEC, the users have the option to configure mbm_total_bytes and mbm_local_bytes to count the specific type of events. Also add configuration instructions with examples. Signed-off-by: Babu Moger --- Documentation/x86/resctrl.rst | 130 +++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 128 insertions(+), 2 deletions(-) diff --git a/Documentation/x86/resctrl.rst b/Documentation/x86/resctrl.rst index 71a531061e4e..b4fe54f219b6 100644 --- a/Documentation/x86/resctrl.rst +++ b/Documentation/x86/resctrl.rst @@ -17,14 +17,16 @@ AMD refers to this feature as AMD Platform Quality of S= ervice(AMD QoS). This feature is enabled by the CONFIG_X86_CPU_RESCTRL and the x86 /proc/cp= uinfo flag bits: =20 -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D RDT (Resource Director Technology) Allocation "rdt_a" CAT (Cache Allocation Technology) "cat_l3", "cat_l2" CDP (Code and Data Prioritization) "cdp_l3", "cdp_l2" CQM (Cache QoS Monitoring) "cqm_llc", "cqm_occup_llc" MBM (Memory Bandwidth Monitoring) "cqm_mbm_total", "cqm_mbm_local" MBA (Memory Bandwidth Allocation) "mba" -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +SMBA (Slow Memory Bandwidth Allocation) "smba" +BMEC (Bandwidth Monitoring Event Configuration) "bmec" +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D =20 To use the feature mount the file system:: =20 @@ -161,6 +163,73 @@ with the following files: "mon_features": Lists the monitoring events if monitoring is enabled for the resource. + Example:: + + # cat /sys/fs/resctrl/info/L3_MON/mon_features + llc_occupancy + mbm_total_bytes + mbm_local_bytes + + If the system supports Bandwidth Monitoring Event + Configuration (BMEC), then the bandwidth events will + be configurable. The output will be:: + + # cat /sys/fs/resctrl/info/L3_MON/mon_features + llc_occupancy + mbm_total_bytes + mbm_total_config + mbm_local_bytes + mbm_local_config + +"mbm_total_config", "mbm_local_config": + These files contain the current event configuration for the events + mbm_total_bytes and mbm_local_bytes, respectively, when the + Bandwidth Monitoring Event Configuration (BMEC) feature is support= ed. + The event configuration settings are domain specific. Changing the + configuration on one CPU in a domain would affect the whole domain. + + Following are the types of events supported: + + =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + Bits Description + =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + 6 Dirty Victims from the QOS domain to all types of memory + 5 Reads to slow memory in the non-local NUMA domain + 4 Reads to slow memory in the local NUMA domain + 3 Non-temporal writes to non-local NUMA domain + 2 Non-temporal writes to local NUMA domain + 1 Reads to memory in the non-local NUMA domain + 0 Reads to memory in the local NUMA domain + =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + + By default, the mbm_total_bytes configuration is set to 0x7f to co= unt + all the event types and the mbm_local_bytes configuration is set to + 0x15 to count all the local memory events. + + Example:: + + To view the current configuration, run the command. + # cat /sys/fs/resctrl/info/L3_MON/mbm_total_config + 0:0x7f;1:0x7f;2:0x7f;3:0x7f + + # cat /sys/fs/resctrl/info/L3_MON/mbm_local_config + 0:0x15;1:0x15;3:0x15;4:0x15 + + To change the mbm_total_bytes to count only reads on domain 0, + run the command. The bits 0,1,4 and 5 needs to set. + + # echo "0:0x33" > /sys/fs/resctrl/info/L3_MON/mbm_total_config + + # cat /sys/fs/resctrl/info/L3_MON/mbm_total_config + 0:0x33;1:0x7f;2:0x7f;3:0x7f + + To change the mbm_local_bytes to count all the slow memory rea= ds on + domain 1, run the command. The bits 4 and 5 needs to set. + + # echo "1:0x30" > /sys/fs/resctrl/info/L3_MON/mbm_local_config + + # cat /sys/fs/resctrl/info/L3_MON/mbm_local_config + 0:0x15;1:0x30;3:0x15;4:0x15 =20 "max_threshold_occupancy": Read/write file provides the largest value (in @@ -264,6 +333,7 @@ When monitoring is enabled all MON groups will also con= tain: the sum for all tasks in the CTRL_MON group and all tasks in MON groups. Please see example section for more details on usage. =20 + Resource allocation rules ------------------------- =20 @@ -464,6 +534,24 @@ Memory bandwidth domain is L3 cache. =20 MB:=3Dbw_MBps0;=3Dbw_MBps1;... =20 +Slow Memory bandwidth Allocation (when supported) +------------------------------------------------- +Currently, CXL.memory is the only supported "slow" memory device. +With the support of SMBA feature the hardware enables bandwidth +allocation on the slow memory devices. If there are multiple slow +memory devices in the system, then the throttling logic groups all +the slow sources together and applies the limit on them as a whole. + +The presence of the SMBA feature(with CXL.memory) is independent +of whether slow memory device is actually present in the system. +If there is no slow memory in the system, then setting a SMBA limit +will have no impact on the performance of the system. + +Slow Memory b/w domain is L3 cache. +:: + + SMBA:=3Dbandwidth0;=3Dbandwidth1;... + Reading/writing the schemata file --------------------------------- Reading the schemata file will show the state of all resources @@ -479,6 +567,44 @@ which you wish to change. E.g. L3DATA:0=3Dfffff;1=3Dfffff;2=3D3c0;3=3Dfffff L3CODE:0=3Dfffff;1=3Dfffff;2=3Dfffff;3=3Dfffff =20 +Reading/writing the schemata file (on AMD systems) +-------------------------------------------------- +Reading the schemata file will show the state of all resources +on all domains. When writing the memory bandwidth allocation you +only need to specify those values in an absolute number expressed +in 1/8 GB/s increments. To allocate bandwidth limit of 2GB, you +need to specify the value 16 (16 * 1/8 =3D 2). E.g. +:: + + # cat schemata + MB:0=3D2048;1=3D2048;2=3D2048;3=3D2048 + L3:0=3Dffff;1=3Dffff;2=3Dffff;3=3Dffff + + # echo "MB:1=3D16" > schemata + # cat schemata + MB:0=3D2048;1=3D 16;2=3D2048;3=3D2048 + L3:0=3Dffff;1=3Dffff;2=3Dffff;3=3Dffff + +Reading/writing the schemata file (on AMD systems) with slow memory +------------------------------------------------------------------- +Reading the schemata file will show the state of all resources +on all domains. When writing the memory bandwidth allocation you +only need to specify those values in an absolute number expressed +in 1/8 GB/s increments. To allocate bandwidth limit of 8GB, you +need to specify the value 64 (64 * 1/8 =3D 8). E.g. +:: + + # cat schemata + SMBA:0=3D2048;1=3D2048;2=3D2048;3=3D2048 + MB:0=3D2048;1=3D2048;2=3D2048;3=3D2048 + L3:0=3Dffff;1=3Dffff;2=3Dffff;3=3Dffff + + # echo "SMBA:1=3D64" > schemata + # cat schemata + SMBA:0=3D2048;1=3D 64;2=3D2048;3=3D2048 + MB:0=3D2048;1=3D2048;2=3D2048;3=3D2048 + L3:0=3Dffff;1=3Dffff;2=3Dffff;3=3Dffff + Cache Pseudo-Locking =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D CAT enables a user to specify the amount of cache space that an