From nobody Sat Jul 27 02:49:23 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4EC61ECAAD8 for ; Fri, 23 Sep 2022 09:59:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232079AbiIWJ7M (ORCPT ); Fri, 23 Sep 2022 05:59:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34644 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231919AbiIWJ7B (ORCPT ); Fri, 23 Sep 2022 05:59:01 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 45795132FDA for ; Fri, 23 Sep 2022 02:58:50 -0700 (PDT) X-UUID: b9acc9701d624861ba749a5e29cfc010-20220923 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=PRn0qWsxaXW+28p/aNbKk48GsaA1Uw9zH6yZFYoTelI=; b=N7CeSQ8u9nmD6+gg8FCyVwh1k4VaFVuDdXkci7llHng7pvfm8dfQ98p9L4q78cGoponwwXmikDilaSjBOlGbfJ20ORekjrCKlzTUWkDAw/N8UHzlsNjvMylYtu9SwfLG+5MxiTRY6XihN4DoYqmTBG5keqM1965Aa0Ak5ZZE/+w=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:115f2ba9-8cc7-47c9-b5f3-2a415554e0df,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:39a5ff1,CLOUDID:7ddddaa2-dc04-435c-b19b-71e131a5fc35,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: b9acc9701d624861ba749a5e29cfc010-20220923 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 997380722; Fri, 23 Sep 2022 17:58:34 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Fri, 23 Sep 2022 17:58:32 +0800 Received: from mszsdaap41.gcn.mediatek.inc (10.16.6.141) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 23 Sep 2022 17:58:31 +0800 From: To: , , , , , , , CC: , , , , , , Xinlei Lee Subject: [PATCH v10,3/3] drm: mediatek: Add mt8186 dpi compatibles and platform data Date: Fri, 23 Sep 2022 17:58:24 +0800 Message-ID: <1663927104-15506-4-git-send-email-xinlei.lee@mediatek.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1663927104-15506-1-git-send-email-xinlei.lee@mediatek.com> References: <1663927104-15506-1-git-send-email-xinlei.lee@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xinlei Lee Add the compatible because use edge_cfg_in_mmsys in mt8186. Signed-off-by: Xinlei Lee Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_dpi.c | 21 +++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++ 2 files changed, 23 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index ad87ecddf58d..325032fd5343 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -941,6 +941,24 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .csc_enable_bit =3D CSC_ENABLE, }; =20 +static const struct mtk_dpi_conf mt8186_conf =3D { + .cal_factor =3D mt8183_calculate_factor, + .reg_h_fre_con =3D 0xe0, + .max_clock_khz =3D 150000, + .output_fmts =3D mt8183_output_fmts, + .num_output_fmts =3D ARRAY_SIZE(mt8183_output_fmts), + .edge_cfg_in_mmsys =3D true, + .pixels_per_iter =3D 1, + .is_ck_de_pol =3D true, + .swap_input_support =3D true, + .support_direct_pin =3D true, + .dimension_mask =3D HPW_MASK, + .hvsize_mask =3D HSIZE_MASK, + .channel_swap_shift =3D CH_SWAP, + .yuv422_en_bit =3D YUV422_EN, + .csc_enable_bit =3D CSC_ENABLE, +}; + static const struct mtk_dpi_conf mt8192_conf =3D { .cal_factor =3D mt8183_calculate_factor, .reg_h_fre_con =3D 0xe0, @@ -1091,6 +1109,9 @@ static const struct of_device_id mtk_dpi_of_ids[] =3D= { { .compatible =3D "mediatek,mt8183-dpi", .data =3D &mt8183_conf, }, + { .compatible =3D "mediatek,mt8186-dpi", + .data =3D &mt8186_conf, + }, { .compatible =3D "mediatek,mt8192-dpi", .data =3D &mt8192_conf, }, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index 546b79412815..3d32fbc66ac1 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -646,6 +646,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = =3D { .data =3D (void *)MTK_DPI }, { .compatible =3D "mediatek,mt8183-dpi", .data =3D (void *)MTK_DPI }, + { .compatible =3D "mediatek,mt8186-dpi", + .data =3D (void *)MTK_DPI }, { .compatible =3D "mediatek,mt8192-dpi", .data =3D (void *)MTK_DPI }, { .compatible =3D "mediatek,mt8195-dp-intf", --=20 2.18.0