From nobody Thu Apr 2 14:48:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A03FCC6FA90 for ; Fri, 23 Sep 2022 06:26:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230089AbiIWG0m (ORCPT ); Fri, 23 Sep 2022 02:26:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46436 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230362AbiIWG0O (ORCPT ); Fri, 23 Sep 2022 02:26:14 -0400 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 94DC912872B; Thu, 22 Sep 2022 23:26:08 -0700 (PDT) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 92A151B67D0; Fri, 23 Sep 2022 08:26:06 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 08D151B67CC; Fri, 23 Sep 2022 08:26:06 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 06C00180031F; Fri, 23 Sep 2022 14:26:03 +0800 (+08) From: Richard Zhu To: l.stach@pengutronix.de, bhelgaas@google.com, robh+dt@kernel.org, lorenzo.pieralisi@arm.com, shawnguo@kernel.org, kishon@ti.com, kw@linux.com, frank.li@nxp.com Cc: hongxing.zhu@nxp.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com Subject: [PATCH v3 12/14] PCI: imx6: Add iMX8MM PCIe EP mode Date: Fri, 23 Sep 2022 14:06:58 +0800 Message-Id: <1663913220-9523-13-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1663913220-9523-1-git-send-email-hongxing.zhu@nxp.com> References: <1663913220-9523-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Based on i.MX8MM platforms, add the i.MX8MM PCIe EP mode support. Signed-off-by: Richard Zhu --- drivers/pci/controller/dwc/pci-imx6.c | 147 +++++++++++++++++++++++--- 1 file changed, 134 insertions(+), 13 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index facc8e7b01c2..1044b0726405 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -52,6 +52,7 @@ enum imx6_pcie_variants { IMX8MQ, IMX8MM, IMX8MP, + IMX8MM_EP, }; =20 #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) @@ -60,6 +61,7 @@ enum imx6_pcie_variants { =20 struct imx6_pcie_drvdata { enum imx6_pcie_variants variant; + enum dw_pcie_device_mode mode; u32 flags; int dbi_length; const char *gpr; @@ -153,23 +155,27 @@ static unsigned int imx6_pcie_grp_offset(const struct= imx6_pcie *imx6_pcie) { WARN_ON(imx6_pcie->drvdata->variant !=3D IMX8MQ && imx6_pcie->drvdata->variant !=3D IMX8MM && + imx6_pcie->drvdata->variant !=3D IMX8MM_EP && imx6_pcie->drvdata->variant !=3D IMX8MP); return imx6_pcie->controller_id =3D=3D 1 ? IOMUXC_GPR16 : IOMUXC_GPR14; } =20 static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie) { - unsigned int mask, val; + unsigned int mask, val, mode; + + if (imx6_pcie->drvdata->mode =3D=3D DW_PCIE_EP_TYPE) + mode =3D PCI_EXP_TYPE_ENDPOINT; + else + mode =3D PCI_EXP_TYPE_ROOT_PORT; =20 if (imx6_pcie->drvdata->variant =3D=3D IMX8MQ && imx6_pcie->controller_id =3D=3D 1) { mask =3D IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE; - val =3D FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, - PCI_EXP_TYPE_ROOT_PORT); + val =3D FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, mode); } else { mask =3D IMX6Q_GPR12_DEVICE_TYPE; - val =3D FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, - PCI_EXP_TYPE_ROOT_PORT); + val =3D FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, mode); } =20 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val); @@ -304,6 +310,7 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_p= cie) { switch (imx6_pcie->drvdata->variant) { case IMX8MM: + case IMX8MM_EP: case IMX8MP: /* * The PHY initialization had been done in the PHY @@ -561,6 +568,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *i= mx6_pcie) case IMX7D: break; case IMX8MM: + case IMX8MM_EP: case IMX8MQ: case IMX8MP: ret =3D clk_prepare_enable(imx6_pcie->pcie_aux); @@ -606,6 +614,7 @@ static void imx6_pcie_disable_ref_clk(struct imx6_pcie = *imx6_pcie) IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); break; case IMX8MM: + case IMX8MM_EP: case IMX8MQ: case IMX8MP: clk_disable_unprepare(imx6_pcie->pcie_aux); @@ -675,6 +684,7 @@ static void imx6_pcie_assert_core_reset(struct imx6_pci= e *imx6_pcie) reset_control_assert(imx6_pcie->pciephy_reset); fallthrough; case IMX8MM: + case IMX8MM_EP: case IMX8MP: reset_control_assert(imx6_pcie->apps_reset); break; @@ -751,6 +761,7 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pc= ie *imx6_pcie) break; case IMX6Q: /* Nothing to do */ case IMX8MM: + case IMX8MM_EP: case IMX8MP: break; } @@ -801,6 +812,7 @@ static void imx6_pcie_ltssm_enable(struct device *dev) case IMX7D: case IMX8MQ: case IMX8MM: + case IMX8MM_EP: case IMX8MP: reset_control_deassert(imx6_pcie->apps_reset); break; @@ -821,6 +833,7 @@ static void imx6_pcie_ltssm_disable(struct device *dev) case IMX7D: case IMX8MQ: case IMX8MM: + case IMX8MM_EP: case IMX8MP: reset_control_assert(imx6_pcie->apps_reset); break; @@ -1002,8 +1015,102 @@ static const struct dw_pcie_host_ops imx6_pcie_host= _ops =3D { =20 static const struct dw_pcie_ops dw_pcie_ops =3D { .start_link =3D imx6_pcie_start_link, + .stop_link =3D imx6_pcie_stop_link, +}; + +static void imx6_pcie_ep_init(struct dw_pcie_ep *ep) +{ + enum pci_barno bar; + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); + + for (bar =3D BAR_0; bar <=3D BAR_5; bar++) + dw_pcie_ep_reset_bar(pci, bar); +} + +static int imx6_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, + enum pci_epc_irq_type type, + u16 interrupt_num) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); + + switch (type) { + case PCI_EPC_IRQ_LEGACY: + return dw_pcie_ep_raise_legacy_irq(ep, func_no); + case PCI_EPC_IRQ_MSI: + return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); + case PCI_EPC_IRQ_MSIX: + return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num); + default: + dev_err(pci->dev, "UNKNOWN IRQ type\n"); + return -EINVAL; + } + + return 0; +} + +static const struct pci_epc_features imx8m_pcie_epc_features =3D { + .linkup_notifier =3D false, + .msi_capable =3D true, + .msix_capable =3D false, + .reserved_bar =3D 1 << BAR_1 | 1 << BAR_3, + .align =3D SZ_64K, +}; + +static const struct pci_epc_features* +imx6_pcie_ep_get_features(struct dw_pcie_ep *ep) +{ + return &imx8m_pcie_epc_features; +} + +static const struct dw_pcie_ep_ops pcie_ep_ops =3D { + .ep_init =3D imx6_pcie_ep_init, + .raise_irq =3D imx6_pcie_ep_raise_irq, + .get_features =3D imx6_pcie_ep_get_features, }; =20 +static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, + struct platform_device *pdev) +{ + int ret; + unsigned int pcie_dbi2_offset; + struct dw_pcie_ep *ep; + struct resource *res; + struct dw_pcie *pci =3D imx6_pcie->pci; + struct dw_pcie_rp *pp =3D &pci->pp; + struct device *dev =3D pci->dev; + + imx6_pcie_host_init(pp); + ep =3D &pci->ep; + ep->ops =3D &pcie_ep_ops; + + switch (imx6_pcie->drvdata->variant) { + case IMX8MM_EP: + pcie_dbi2_offset =3D SZ_1M; + break; + default: + pcie_dbi2_offset =3D SZ_4K; + break; + } + pci->dbi_base2 =3D pci->dbi_base + pcie_dbi2_offset; + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); + if (!res) + return -EINVAL; + + ep->phys_base =3D res->start; + ep->addr_size =3D resource_size(res); + ep->page_size =3D SZ_64K; + + ret =3D dw_pcie_ep_init(ep); + if (ret) { + dev_err(dev, "failed to initialize endpoint\n"); + return ret; + } + /* Start LTSSM. */ + imx6_pcie_ltssm_enable(dev); + + return 0; +} + static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie) { struct device *dev =3D imx6_pcie->pci->dev; @@ -1189,6 +1296,7 @@ static int imx6_pcie_probe(struct platform_device *pd= ev) } break; case IMX8MM: + case IMX8MM_EP: case IMX8MP: imx6_pcie->pcie_aux =3D devm_clk_get(dev, "pcie_aux"); if (IS_ERR(imx6_pcie->pcie_aux)) @@ -1278,15 +1386,22 @@ static int imx6_pcie_probe(struct platform_device *= pdev) if (ret) return ret; =20 - ret =3D dw_pcie_host_init(&pci->pp); - if (ret < 0) - return ret; + if (imx6_pcie->drvdata->mode =3D=3D DW_PCIE_EP_TYPE) { + ret =3D imx6_add_pcie_ep(imx6_pcie, pdev); + if (ret < 0) + return ret; + } else { + ret =3D dw_pcie_host_init(&pci->pp); + if (ret < 0) + return ret; + + if (pci_msi_enabled()) { + u8 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); =20 - if (pci_msi_enabled()) { - u8 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); - val =3D dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS); - val |=3D PCI_MSI_FLAGS_ENABLE; - dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val); + val =3D dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS); + val |=3D PCI_MSI_FLAGS_ENABLE; + dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val); + } } =20 return 0; @@ -1342,6 +1457,11 @@ static const struct imx6_pcie_drvdata drvdata[] =3D { .flags =3D IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, .gpr =3D "fsl,imx8mp-iomuxc-gpr", }, + [IMX8MM_EP] =3D { + .variant =3D IMX8MM_EP, + .mode =3D DW_PCIE_EP_TYPE, + .gpr =3D "fsl,imx8mm-iomuxc-gpr", + }, }; =20 static const struct of_device_id imx6_pcie_of_match[] =3D { @@ -1352,6 +1472,7 @@ static const struct of_device_id imx6_pcie_of_match[]= =3D { { .compatible =3D "fsl,imx8mq-pcie", .data =3D &drvdata[IMX8MQ], }, { .compatible =3D "fsl,imx8mm-pcie", .data =3D &drvdata[IMX8MM], }, { .compatible =3D "fsl,imx8mp-pcie", .data =3D &drvdata[IMX8MP], }, + { .compatible =3D "fsl,imx8mm-pcie-ep", .data =3D &drvdata[IMX8MM_EP], }, {}, }; =20 --=20 2.25.1