From nobody Sat Sep 21 14:11:04 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A41D1C6FA8B for ; Thu, 22 Sep 2022 07:30:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231195AbiIVHaI (ORCPT ); Thu, 22 Sep 2022 03:30:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231133AbiIVH3r (ORCPT ); Thu, 22 Sep 2022 03:29:47 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B08C61DAA for ; Thu, 22 Sep 2022 00:29:44 -0700 (PDT) X-UUID: c69c8cd534b04496a4f5a91931bacf51-20220922 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=3nuqawZO/oysx683uHs52mHGHfy7Wf+8CTWtHYZPslY=; b=cTfbohB2B1ima4diY8dB265PlT0Je0MrT4JpJNbjXPVUPlE3ZUzhKLENsZElVi/wpeWob89jUUVglwla36nGdlSnMXY70Xdn/AuyKGDW1DPZjyYOUI2hay3CPaNPyYavi1gxYzsjPMZiypZOJ2fGtCeCUzXoXeUj4HVnnFoQ30Q=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:df199a26-b779-46fd-946b-ff1fb805673a,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:70 X-CID-INFO: VERSION:1.1.11,REQID:df199a26-b779-46fd-946b-ff1fb805673a,IP:0,URL :0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTI ON:quarantine,TS:70 X-CID-META: VersionHash:39a5ff1,CLOUDID:a5a5a706-1cee-4c38-b21b-a45f9682fdc0,B ulkID:220922152940IA7ZNPK4,BulkQuantity:0,Recheck:0,SF:28|17|19|48|823|824 ,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL :0 X-UUID: c69c8cd534b04496a4f5a91931bacf51-20220922 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1036245463; Thu, 22 Sep 2022 15:29:38 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Thu, 22 Sep 2022 15:29:36 +0800 Received: from mszsdaap41.gcn.mediatek.inc (10.16.6.141) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 22 Sep 2022 15:29:36 +0800 From: To: , , , , , , , CC: , , , , , , Xinlei Lee Subject: [PATCH v7,3/3] drm: mediatek: Add mt8186 dpi compatible to Date: Thu, 22 Sep 2022 15:29:24 +0800 Message-ID: <1663831764-18169-4-git-send-email-xinlei.lee@mediatek.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1663831764-18169-1-git-send-email-xinlei.lee@mediatek.com> References: <1663831764-18169-1-git-send-email-xinlei.lee@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xinlei Lee Add the compatible because use edge_cfg_in_mmsys in mt8186. Signed-off-by: Xinlei Lee --- drivers/gpu/drm/mediatek/mtk_dpi.c | 21 +++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++ 2 files changed, 23 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index bd1870a8504a..2fcf7a61c340 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -941,6 +941,24 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .csc_enable_bit =3D CSC_ENABLE, }; =20 +static const struct mtk_dpi_conf mt8186_conf =3D { + .cal_factor =3D mt8183_calculate_factor, + .reg_h_fre_con =3D 0xe0, + .max_clock_khz =3D 150000, + .output_fmts =3D mt8183_output_fmts, + .num_output_fmts =3D ARRAY_SIZE(mt8183_output_fmts), + .edge_cfg_in_mmsys =3D true, + .pixels_per_iter =3D 1, + .is_ck_de_pol =3D true, + .swap_input_support =3D true, + .support_direct_pin =3D true, + .dimension_mask =3D HPW_MASK, + .hvsize_mask =3D HSIZE_MASK, + .channel_swap_shift =3D CH_SWAP, + .yuv422_en_bit =3D YUV422_EN, + .csc_enable_bit =3D CSC_ENABLE, +}; + static const struct mtk_dpi_conf mt8192_conf =3D { .cal_factor =3D mt8183_calculate_factor, .reg_h_fre_con =3D 0xe0, @@ -1091,6 +1109,9 @@ static const struct of_device_id mtk_dpi_of_ids[] =3D= { { .compatible =3D "mediatek,mt8183-dpi", .data =3D &mt8183_conf, }, + { .compatible =3D "mediatek,mt8186-dpi", + .data =3D &mt8186_conf, + }, { .compatible =3D "mediatek,mt8192-dpi", .data =3D &mt8192_conf, }, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index 546b79412815..3d32fbc66ac1 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -646,6 +646,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = =3D { .data =3D (void *)MTK_DPI }, { .compatible =3D "mediatek,mt8183-dpi", .data =3D (void *)MTK_DPI }, + { .compatible =3D "mediatek,mt8186-dpi", + .data =3D (void *)MTK_DPI }, { .compatible =3D "mediatek,mt8192-dpi", .data =3D (void *)MTK_DPI }, { .compatible =3D "mediatek,mt8195-dp-intf", --=20 2.18.0