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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT090.mail.protection.outlook.com (10.13.177.105) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5612.13 via Frontend Transport; Wed, 7 Sep 2022 17:59:59 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Wed, 7 Sep 2022 12:59:57 -0500 Subject: [PATCH v4 01/13] x86/resctrl: Fix min_cbm_bits for AMD From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Wed, 7 Sep 2022 12:59:56 -0500 Message-ID: <166257359679.1043018.9253512972611409799.stgit@bmoger-ubuntu> In-Reply-To: <166257348081.1043018.11227924488792315932.stgit@bmoger-ubuntu> References: <166257348081.1043018.11227924488792315932.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Sep 2022 17:59:59.0293 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 682b66a4-f66e-4acc-bd0e-08da90fac793 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT090.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6363 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org AMD systems support zero CBM (capacity bit mask) for L3 allocation. That is reflected in rdt_init_res_defs_amd() by: r->cache.arch_has_empty_bitmaps =3D true; However given the unified code in cbm_validate(), checking for: val =3D=3D 0 && !arch_has_empty_bitmaps is not enough because of another check in cbm_validate(): if ((zero_bit - first_bit) < r->cache.min_cbm_bits) The default value of r->cache.min_cbm_bits =3D 1. Leading to: $ cd /sys/fs/resctrl $ mkdir foo $ cd foo $ echo L3:0=3D0 > schemata -bash: echo: write error: Invalid argument $ cat /sys/fs/resctrl/info/last_cmd_status Need at least 1 bits in the mask Fix the issue by initializing the min_cbm_bits to 0 for AMD. Also, remove the default setting of min_cbm_bits and initialize it separately. After the fix $ cd /sys/fs/resctrl $ mkdir foo $ cd foo $ echo L3:0=3D0 > schemata $ cat /sys/fs/resctrl/info/last_cmd_status ok Link: https://lore.kernel.org/lkml/20220517001234.3137157-1-eranian@google.= com/ Fixes: 316e7f901f5a ("x86/resctrl: Add struct rdt_cache::arch_has_{sparse, = empty}_bitmaps") Signed-off-by: Stephane Eranian Signed-off-by: Babu Moger Reviewed-by: Ingo Molnar Reviewed-by: James Morse Reviewed-by: Reinette Chatre --- arch/x86/kernel/cpu/resctrl/core.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index bb1c3f5f60c8..a5c51a14fbce 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -66,9 +66,6 @@ struct rdt_hw_resource rdt_resources_all[] =3D { .rid =3D RDT_RESOURCE_L3, .name =3D "L3", .cache_level =3D 3, - .cache =3D { - .min_cbm_bits =3D 1, - }, .domains =3D domain_init(RDT_RESOURCE_L3), .parse_ctrlval =3D parse_cbm, .format_str =3D "%d=3D%0*x", @@ -83,9 +80,6 @@ struct rdt_hw_resource rdt_resources_all[] =3D { .rid =3D RDT_RESOURCE_L2, .name =3D "L2", .cache_level =3D 2, - .cache =3D { - .min_cbm_bits =3D 1, - }, .domains =3D domain_init(RDT_RESOURCE_L2), .parse_ctrlval =3D parse_cbm, .format_str =3D "%d=3D%0*x", @@ -877,6 +871,7 @@ static __init void rdt_init_res_defs_intel(void) r->cache.arch_has_sparse_bitmaps =3D false; r->cache.arch_has_empty_bitmaps =3D false; r->cache.arch_has_per_cpu_cfg =3D false; + r->cache.min_cbm_bits =3D 1; } else if (r->rid =3D=3D RDT_RESOURCE_MBA) { hw_res->msr_base =3D MSR_IA32_MBA_THRTL_BASE; hw_res->msr_update =3D mba_wrmsr_intel; @@ -897,6 +892,7 @@ static __init void rdt_init_res_defs_amd(void) r->cache.arch_has_sparse_bitmaps =3D true; r->cache.arch_has_empty_bitmaps =3D true; r->cache.arch_has_per_cpu_cfg =3D true; + r->cache.min_cbm_bits =3D 0; } else if (r->rid =3D=3D RDT_RESOURCE_MBA) { hw_res->msr_base =3D MSR_IA32_MBA_BW_BASE; hw_res->msr_update =3D mba_wrmsr_amd; From nobody Fri Apr 10 15:42:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46FCCC54EE9 for ; Wed, 7 Sep 2022 18:00:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230156AbiIGSA1 (ORCPT ); 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Wed, 7 Sep 2022 13:00:09 -0500 Subject: [PATCH v4 02/13] x86/resctrl: Remove arch_has_empty_bitmaps From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Wed, 7 Sep 2022 13:00:03 -0500 Message-ID: <166257360370.1043018.10126722515228365580.stgit@bmoger-ubuntu> In-Reply-To: <166257348081.1043018.11227924488792315932.stgit@bmoger-ubuntu> References: <166257348081.1043018.11227924488792315932.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT041:EE_|SJ1PR12MB6242:EE_ X-MS-Office365-Filtering-Correlation-Id: ffd31fa0-ca86-4df5-9934-08da90faceb6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Sep 2022 18:00:10.9862 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ffd31fa0-ca86-4df5-9934-08da90faceb6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT041.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6242 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The field arch_has_empty_bitmaps is not required anymore. The field min_cbm_bits is enough to validate the CBM (capacity bit mask) if the architecture can support the zero CBM or not. Suggested-by: Reinette Chatre Signed-off-by: Babu Moger Reviewed-by: Reinette Chatre --- arch/x86/kernel/cpu/resctrl/core.c | 2 -- arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 3 +-- include/linux/resctrl.h | 6 +++--- 3 files changed, 4 insertions(+), 7 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index a5c51a14fbce..c2657754672e 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -869,7 +869,6 @@ static __init void rdt_init_res_defs_intel(void) if (r->rid =3D=3D RDT_RESOURCE_L3 || r->rid =3D=3D RDT_RESOURCE_L2) { r->cache.arch_has_sparse_bitmaps =3D false; - r->cache.arch_has_empty_bitmaps =3D false; r->cache.arch_has_per_cpu_cfg =3D false; r->cache.min_cbm_bits =3D 1; } else if (r->rid =3D=3D RDT_RESOURCE_MBA) { @@ -890,7 +889,6 @@ static __init void rdt_init_res_defs_amd(void) if (r->rid =3D=3D RDT_RESOURCE_L3 || r->rid =3D=3D RDT_RESOURCE_L2) { r->cache.arch_has_sparse_bitmaps =3D true; - r->cache.arch_has_empty_bitmaps =3D true; r->cache.arch_has_per_cpu_cfg =3D true; r->cache.min_cbm_bits =3D 0; } else if (r->rid =3D=3D RDT_RESOURCE_MBA) { diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cp= u/resctrl/ctrlmondata.c index 87666275eed9..7f38c8bd8429 100644 --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c @@ -98,8 +98,7 @@ static bool cbm_validate(char *buf, u32 *data, struct rdt= _resource *r) return false; } =20 - if ((!r->cache.arch_has_empty_bitmaps && val =3D=3D 0) || - val > r->default_ctrl) { + if ((r->cache.min_cbm_bits > 0 && val =3D=3D 0) || val > r->default_ctrl)= { rdt_last_cmd_puts("Mask out of range\n"); return false; } diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index 21deb5212bbd..46ed8589857c 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -72,11 +72,12 @@ struct rdt_domain { /** * struct resctrl_cache - Cache allocation related data * @cbm_len: Length of the cache bit mask - * @min_cbm_bits: Minimum number of consecutive bits to be set + * @min_cbm_bits: Minimum number of consecutive bits to be set. + * The value 0 means the architecture can support + * zero CBM. * @shareable_bits: Bitmask of shareable resource with other * executing entities * @arch_has_sparse_bitmaps: True if a bitmap like f00f is valid. - * @arch_has_empty_bitmaps: True if the '0' bitmap is valid. * @arch_has_per_cpu_cfg: True if QOS_CFG register for this cache * level has CPU scope. */ @@ -85,7 +86,6 @@ struct resctrl_cache { unsigned int min_cbm_bits; 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Wed, 7 Sep 2022 18:00:23 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT074.mail.protection.outlook.com (10.13.176.154) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5612.13 via Frontend Transport; Wed, 7 Sep 2022 18:00:23 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Wed, 7 Sep 2022 13:00:21 -0500 Subject: [PATCH v4 03/13] x86/cpufeatures: Add Slow Memory Bandwidth Allocation feature flag From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Wed, 7 Sep 2022 13:00:15 -0500 Message-ID: <166257361558.1043018.12046795385220064687.stgit@bmoger-ubuntu> In-Reply-To: <166257348081.1043018.11227924488792315932.stgit@bmoger-ubuntu> References: <166257348081.1043018.11227924488792315932.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Sep 2022 18:00:23.5539 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 07ccbdb9-83a1-44b0-e734-08da90fad631 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT074.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6308 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Adds the new AMD feature X86_FEATURE_SMBA. With this feature, the QOS enforcement policies can be applied to external slow memory connected to the host. QOS enforcement is accomplished by assigning a Class Of Service (COS) to a processor and specifying allocations or limits for that COS for each resource to be allocated. This feature is identified by the CPUID Function 8000_0020_EBX_x0. CPUID Fn8000_0020_EBX_x0 AMD Bandwidth Enforcement Feature Identifiers (ECX= =3D0) Bits Field Name Description 2 L3SBE L3 external slow memory bandwidth enforcement Currently, CXL.memory is the only supported "slow" memory device. With the support of SMBA feature the hardware enables bandwidth allocation on the slow memory devices. If there are multiple slow memory devices in the syste= m, then the throttling logic groups all the slow sources together and applies the limit on them as a whole. The presence of the SMBA feature(with CXL.memory) is independent of whether slow memory device is actually present in the system. If there is no slow memory in the system, then setting a SMBA limit will have no impact on the performance of the system. Presence of CXL memory can be identified by numactl command. $numactl -H available: 2 nodes (0-1) node 0 cpus: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 node 0 size: 63678 MB node 0 free: 59542 MB node 1 cpus: node 1 size: 16122 MB node 1 free: 15627 MB node distances: node 0 1 0: 10 50 1: 50 10 CPU list for CXL memory will be emply. The cpu-cxl node distance is greater than cpu-to-cpu distances. Node 1 has the CXL memory in this case. CXL memory can also be identified using ACPI SRAT table and memory maps. Feature description is available in the specification, "AMD64 Technology Pl= atform Quality of Service Extensions, Revision: 1.03 Publication # 56375 Revision: 1.03 Is= sue Date: February 2022". Link: https://www.amd.com/en/support/tech-docs/amd64-technology-platform-qu= ality-service-extensions Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/scattered.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 235dc85c91c3..1815435c9c88 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -304,6 +304,7 @@ #define X86_FEATURE_UNRET (11*32+15) /* "" AMD BTB untrain return */ #define X86_FEATURE_USE_IBPB_FW (11*32+16) /* "" Use IBPB during runtime = firmware calls */ #define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM exit w= hen EIBRS is enabled */ +#define X86_FEATURE_SMBA (11*32+18) /* SLOW Memory Bandwidth Allocation */ =20 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c index fd44b54c90d5..885ecf46abb2 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -44,6 +44,7 @@ static const struct cpuid_bit cpuid_bits[] =3D { { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 }, { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, + { X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 }, { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, { 0, 0, 0, 0, 0 } }; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Sep 2022 18:00:29.6121 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6e16b257-11a1-44c1-4f58-08da90fad9ce X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT049.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4938 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Adds a new resource type RDT_RESOURCE_SMBA to handle the QoS enforcement policies on the external slow memory. Signed-off-by: Babu Moger --- arch/x86/kernel/cpu/resctrl/core.c | 12 ++++++++++++ arch/x86/kernel/cpu/resctrl/internal.h | 1 + 2 files changed, 13 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index c2657754672e..a7e9aabff8c8 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -100,6 +100,18 @@ struct rdt_hw_resource rdt_resources_all[] =3D { .fflags =3D RFTYPE_RES_MB, }, }, + [RDT_RESOURCE_SMBA] =3D + { + .r_resctrl =3D { + .rid =3D RDT_RESOURCE_SMBA, + .name =3D "SMBA", + .cache_level =3D 3, + .domains =3D domain_init(RDT_RESOURCE_SMBA), + .parse_ctrlval =3D parse_bw, + .format_str =3D "%d=3D%*u", + .fflags =3D RFTYPE_RES_MB, + }, + }, }; =20 /* diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 1d647188a43b..24a1dfeb6cb2 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -418,6 +418,7 @@ enum resctrl_res_level { RDT_RESOURCE_L3, RDT_RESOURCE_L2, RDT_RESOURCE_MBA, + RDT_RESOURCE_SMBA, =20 /* Must be the last */ RDT_NUM_RESOURCES, From nobody Fri Apr 10 15:42:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9DCEC6FA86 for ; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT049:EE_|BY5PR12MB5000:EE_ X-MS-Office365-Filtering-Correlation-Id: 31371517-703d-4b48-bffc-08da90fadddd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 4QahFTe6E10NtHdpXEbDVnlSoR62gGEQ8wiPB2S/o/A2higBT/k1W/zNvb7aBX4NwYCTeVVynLW7IpmufOFcfukZO3wy6rgH1adZDWU1ZoVfSbBirWeTP7VSDb/AsOw68bOzupXYtz5B7S2MzRJdJerApSjXUF85aQm6nH7snEArlPDvGmQn2LAAhBX8MZmz38loxMVWBKuAYp6Uuoh2b063Xd+mS5CfLc15FGxR/WelhS3R3vGy7fJlj8FbcJGhAkwu/V4MziKsmze4p3vnOXlP1rFanmsghlJD95RyW0a9Rt8GLzA8AtDJx6DcR5axAKzu+m/SDNW0V0U6YOMQtM163hMB5E8ZF7C53kfz+XWw1AD3/SUhmdrYzVniLBG6uAXLq95kmdOzP+1f4LFPpkGrqMstO02PDIbbUw8m6yyYjtqR0W/mkfCoMwwcfKsvTlx3TJLV6sYtB8H7KFtekTSVeXYVvyTq0mIXmJ/MX6NSg90No4jHvv3g1SpJ/kIiMUg7fTf6trLiSoT8XaXKQp3lW/AvdVltDPP7D7/Ffi7WlwJlcx6BF08i2LN7vqEpAK9uDPqxGZuZ1OkJxSM5UWpKafYE0hjGPSG00Ucgbr4U3/PU6V84KkblO+yJBh8Wfung98tSasQeb6YNklpj3rT4VEYnxBTvwXJZ/319LRW/4OfxGXYlO1J120m0wfCFQLqVIwSplDVqx/5DKSef3JG3bUhoD5jVYOTGVbR849yaRb0EeHElIliv1MI+gUkdWYhHN4kHbCTn1Lpu9P3+GEKz70fA+tXPyElyZxXdZ8+RocYrNSJIhgHmi2Yicf+e2iMA4x8XrjnHhmlbvwM1fx0IXeWSaSYFAGKZNvd6wOqgDjXIWTpYfzeYqC0OPg0ywt1OBfhfe8niJH8I+RidmA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230016)(7916004)(4636009)(396003)(136003)(346002)(376002)(39860400002)(36840700001)(40470700004)(46966006)(186003)(82740400003)(9686003)(81166007)(356005)(2906002)(4326008)(82310400005)(316002)(110136005)(54906003)(16576012)(26005)(8936002)(478600001)(40480700001)(86362001)(426003)(8676002)(44832011)(7416002)(70206006)(33716001)(36860700001)(103116003)(40460700003)(83380400001)(47076005)(5660300002)(966005)(16526019)(70586007)(336012)(41300700001)(71626007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Sep 2022 18:00:36.4242 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 31371517-703d-4b48-bffc-08da90fadddd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT049.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB5000 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Newer AMD processors support the new feature Bandwidth Monitoring Event Configuration (BMEC). Support of this feature is available via CPUID Fn8000_0020_EBX_x0 (ECX=3D0). Bits Field Name Description 3 EVT_CFG Bandwidth Monitoring Event Configuration (BMEC) Currently, the bandwidth monitoring events mbm_total_bytes and mbm_local_bytes are set to count all the total and local reads/writes respectively. With the introduction of SLOW memory, the two counters are not enough to count all the different types of memory events. With the feature BMEC, the users have the option to configure mbm_total_bytes and mbm_local_bytes to count the specific type of events. Each BMEC event has a configuration MSR, QOS_EVT_CFG (0x000_0400h + EventID) which contains one field for each Bandwidth Type that can be used to configure the bandwidth event to track any combination of supported bandwidth types. The event will count requests from every Bandwidth Type bit that is set in the corresponding configuration register. Following are the types of events supported: =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Bits Description =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D 6 Dirty Victims from the QOS domain to all types of memory 5 Reads to slow memory in the non-local NUMA domain 4 Reads to slow memory in the local NUMA domain 3 Non-temporal writes to non-local NUMA domain 2 Non-temporal writes to local NUMA domain 1 Reads to memory in the non-local NUMA domain 0 Reads to memory in the local NUMA domain =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D By default, the mbm_total_bytes configuration is set to 0x7F to count all the event types and the mbm_local_bytes configuration is set to 0x15 to count all the local memory events. Feature description is available in the specification, "AMD64 Technology Platform Quality of Service Extensions, Revision: 1.03 Publication # 56375 Revision: 1.03 Issue Date: February 2022". Link: https://www.amd.com/en/support/tech-docs/amd64-technology-platform-qu= ality-service-extensions Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger Reviewed-by: Ingo Molnar --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/scattered.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 1815435c9c88..a4ee02a56d54 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -305,6 +305,7 @@ #define X86_FEATURE_USE_IBPB_FW (11*32+16) /* "" Use IBPB during runtime = firmware calls */ #define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM exit w= hen EIBRS is enabled */ #define X86_FEATURE_SMBA (11*32+18) /* SLOW Memory Bandwidth Allocation */ +#define X86_FEATURE_BMEC (11*32+18) /* AMD Bandwidth Monitoring Event Con= figuration (BMEC) */ =20 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c index 885ecf46abb2..7981df0b910e 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -45,6 +45,7 @@ static const struct cpuid_bit cpuid_bits[] =3D { { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, { X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 }, + { X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 }, { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, { 0, 0, 0, 0, 0 } }; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT099.mail.protection.outlook.com (10.13.177.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5612.13 via Frontend Transport; Wed, 7 Sep 2022 18:00:43 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Wed, 7 Sep 2022 13:00:41 -0500 Subject: [PATCH v4 06/13] x86/resctrl: Include new features in command line options From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Wed, 7 Sep 2022 13:00:41 -0500 Message-ID: <166257364128.1043018.12636485490608845145.stgit@bmoger-ubuntu> In-Reply-To: <166257348081.1043018.11227924488792315932.stgit@bmoger-ubuntu> References: <166257348081.1043018.11227924488792315932.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Sep 2022 18:00:43.7484 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ffaee25c-60fe-4199-56b1-08da90fae23b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT099.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6293 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the command line options to disable the new features. smba : Slow Memory Bandwidth Allocation mbec : Bandwidth Monitor Event Configuration. Signed-off-by: Babu Moger --- Documentation/admin-guide/kernel-parameters.txt | 2 +- arch/x86/kernel/cpu/resctrl/core.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index d7f30902fda0..c109fecb93ea 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -5169,7 +5169,7 @@ rdt=3D [HW,X86,RDT] Turn on/off individual RDT features. List is: cmt, mbmtotal, mbmlocal, l3cat, l3cdp, l2cat, l2cdp, - mba. + mba, smba, bmec. E.g. to turn on cmt and turn off mba use: rdt=3Dcmt,!mba =20 diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index a7e9aabff8c8..53fbc3acad81 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -700,6 +700,8 @@ enum { RDT_FLAG_L2_CAT, RDT_FLAG_L2_CDP, RDT_FLAG_MBA, + RDT_FLAG_SMBA, + RDT_FLAG_BMEC, }; =20 #define RDT_OPT(idx, n, f) \ @@ -723,6 +725,8 @@ static struct rdt_options rdt_options[] __initdata =3D= { RDT_OPT(RDT_FLAG_L2_CAT, "l2cat", X86_FEATURE_CAT_L2), RDT_OPT(RDT_FLAG_L2_CDP, "l2cdp", X86_FEATURE_CDP_L2), RDT_OPT(RDT_FLAG_MBA, "mba", X86_FEATURE_MBA), + RDT_OPT(RDT_FLAG_SMBA, "smba", X86_FEATURE_SMBA), + RDT_OPT(RDT_FLAG_BMEC, "bmec", X86_FEATURE_BMEC), }; #define NUM_RDT_OPTIONS ARRAY_SIZE(rdt_options) =20 From nobody Fri Apr 10 15:42:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9EA3DC54EE9 for ; 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Received-SPF: TempError (protection.outlook.com: error in processing during lookup of amd.com: DNS Timeout) Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000B8ED.mail.protection.outlook.com (10.167.241.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5612.10 via Frontend Transport; Wed, 7 Sep 2022 18:00:54 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Wed, 7 Sep 2022 13:00:48 -0500 Subject: [PATCH v4 07/13] x86/resctrl: Detect and configure Slow Memory Bandwidth allocation From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Wed, 7 Sep 2022 13:00:48 -0500 Message-ID: <166257364828.1043018.1517644566865821019.stgit@bmoger-ubuntu> In-Reply-To: <166257348081.1043018.11227924488792315932.stgit@bmoger-ubuntu> References: <166257348081.1043018.11227924488792315932.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Sep 2022 18:00:54.0666 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f980c5b0-d8c4-42d6-82f2-08da90fb1171 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000B8ED.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4067 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The QoS slow memory configuration details are available via CPUID_Fn80000020_EDX_x02. Detect the available details and initialize the rest to defaults. Signed-off-by: Babu Moger --- arch/x86/kernel/cpu/resctrl/core.c | 29 +++++++++++++++++++++++++= ++-- arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 2 +- arch/x86/kernel/cpu/resctrl/internal.h | 1 + arch/x86/kernel/cpu/resctrl/rdtgroup.c | 9 ++++++--- 4 files changed, 35 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 53fbc3acad81..56c96607259c 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -227,9 +227,15 @@ static bool __rdt_get_mem_config_amd(struct rdt_resour= ce *r) struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r); union cpuid_0x10_3_eax eax; union cpuid_0x10_x_edx edx; - u32 ebx, ecx; + u32 ebx, ecx, subleaf; + + /* + * Query CPUID_Fn80000020_EDX_x01 for MBA and + * CPUID_Fn80000020_EDX_x02 for SMBA + */ + subleaf =3D (r->rid =3D=3D RDT_RESOURCE_SMBA) ? 2 : 1; =20 - cpuid_count(0x80000020, 1, &eax.full, &ebx, &ecx, &edx.full); + cpuid_count(0x80000020, subleaf, &eax.full, &ebx, &ecx, &edx.full); hw_res->num_closid =3D edx.split.cos_max + 1; r->default_ctrl =3D MAX_MBA_BW_AMD; =20 @@ -791,6 +797,19 @@ static __init bool get_mem_config(void) return false; } =20 +static __init bool get_slow_mem_config(void) +{ + struct rdt_hw_resource *hw_res =3D &rdt_resources_all[RDT_RESOURCE_SMBA]; + + if (!rdt_cpu_has(X86_FEATURE_SMBA)) + return false; + + if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD) + return __rdt_get_mem_config_amd(&hw_res->r_resctrl); + + return false; +} + static __init bool get_rdt_alloc_resources(void) { struct rdt_resource *r; @@ -821,6 +840,9 @@ static __init bool get_rdt_alloc_resources(void) if (get_mem_config()) ret =3D true; =20 + if (get_slow_mem_config()) + ret =3D true; + return ret; } =20 @@ -910,6 +932,9 @@ static __init void rdt_init_res_defs_amd(void) } else if (r->rid =3D=3D RDT_RESOURCE_MBA) { hw_res->msr_base =3D MSR_IA32_MBA_BW_BASE; hw_res->msr_update =3D mba_wrmsr_amd; + } else if (r->rid =3D=3D RDT_RESOURCE_SMBA) { + hw_res->msr_base =3D MSR_IA32_SMBA_BW_BASE; + hw_res->msr_update =3D mba_wrmsr_amd; } } } diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cp= u/resctrl/ctrlmondata.c index 7f38c8bd8429..480600b8e4cf 100644 --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c @@ -202,7 +202,7 @@ static int parse_line(char *line, struct resctrl_schema= *s, unsigned long dom_id; =20 if (rdtgrp->mode =3D=3D RDT_MODE_PSEUDO_LOCKSETUP && - r->rid =3D=3D RDT_RESOURCE_MBA) { + (r->rid =3D=3D RDT_RESOURCE_MBA || r->rid =3D=3D RDT_RESOURCE_SMBA)) { rdt_last_cmd_puts("Cannot pseudo-lock MBA resource\n"); return -EINVAL; } diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 24a1dfeb6cb2..c049a274383c 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -14,6 +14,7 @@ #define MSR_IA32_L2_CBM_BASE 0xd10 #define MSR_IA32_MBA_THRTL_BASE 0xd50 #define MSR_IA32_MBA_BW_BASE 0xc0000200 +#define MSR_IA32_SMBA_BW_BASE 0xc0000280 =20 #define MSR_IA32_QM_CTR 0x0c8e #define MSR_IA32_QM_EVTSEL 0x0c8d diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index f276aff521e8..fc5286067201 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1218,7 +1218,7 @@ static bool rdtgroup_mode_test_exclusive(struct rdtgr= oup *rdtgrp) =20 list_for_each_entry(s, &resctrl_schema_all, list) { r =3D s->res; - if (r->rid =3D=3D RDT_RESOURCE_MBA) + if (r->rid =3D=3D RDT_RESOURCE_MBA || r->rid =3D=3D RDT_RESOURCE_SMBA) continue; has_cache =3D true; list_for_each_entry(d, &r->domains, list) { @@ -1399,7 +1399,8 @@ static int rdtgroup_size_show(struct kernfs_open_file= *of, ctrl =3D resctrl_arch_get_config(r, d, rdtgrp->closid, schema->conf_type); - if (r->rid =3D=3D RDT_RESOURCE_MBA) + if (r->rid =3D=3D RDT_RESOURCE_MBA || + r->rid =3D=3D RDT_RESOURCE_SMBA) size =3D ctrl; else size =3D rdtgroup_cbm_to_size(r, d, ctrl); @@ -2807,7 +2808,9 @@ static int rdtgroup_init_alloc(struct rdtgroup *rdtgr= p) =20 list_for_each_entry(s, &resctrl_schema_all, list) { r =3D s->res; - if (r->rid =3D=3D RDT_RESOURCE_MBA) { + if (r->rid =3D=3D RDT_RESOURCE_MBA || + r->rid =3D=3D RDT_RESOURCE_SMBA) { + rdtgroup_init_mba(r); } else { ret =3D rdtgroup_init_cat(s, rdtgrp->closid); From nobody Fri Apr 10 15:42:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06EBBC54EE9 for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT116.mail.protection.outlook.com (10.13.176.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5612.13 via Frontend Transport; Wed, 7 Sep 2022 18:01:07 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Wed, 7 Sep 2022 13:00:55 -0500 Subject: [PATCH v4 08/13] x86/resctrl : Introduce data structure to support monitor configuration From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Wed, 7 Sep 2022 13:00:55 -0500 Message-ID: <166257365519.1043018.5600209070890797172.stgit@bmoger-ubuntu> In-Reply-To: <166257348081.1043018.11227924488792315932.stgit@bmoger-ubuntu> References: <166257348081.1043018.11227924488792315932.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Sep 2022 18:01:07.3193 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f04d9356-1b11-4a99-f89d-08da90faf047 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT116.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4342 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add couple of fields in mon_evt to support Bandwidth Monitoring Event Configuratio (BMEC) and also update the "mon_features". The sysfs file "mon_features" will display the monitor configuration if supported. Before the change. $cat /sys/fs/resctrl/info/L3_MON/mon_features llc_occupancy mbm_total_bytes mbm_local_bytes After the change if BMEC is supported. $cat /sys/fs/resctrl/info/L3_MON/mon_features llc_occupancy mbm_total_bytes mbm_total_config mbm_local_bytes mbm_local_config Signed-off-by: Babu Moger --- arch/x86/kernel/cpu/resctrl/core.c | 3 ++- arch/x86/kernel/cpu/resctrl/internal.h | 6 +++++- arch/x86/kernel/cpu/resctrl/monitor.c | 9 ++++++++- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 5 ++++- 4 files changed, 19 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 56c96607259c..513e6a00f58e 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -849,6 +849,7 @@ static __init bool get_rdt_alloc_resources(void) static __init bool get_rdt_mon_resources(void) { struct rdt_resource *r =3D &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl; + bool mon_configurable =3D rdt_cpu_has(X86_FEATURE_BMEC); =20 if (rdt_cpu_has(X86_FEATURE_CQM_OCCUP_LLC)) rdt_mon_features |=3D (1 << QOS_L3_OCCUP_EVENT_ID); @@ -860,7 +861,7 @@ static __init bool get_rdt_mon_resources(void) if (!rdt_mon_features) return false; =20 - return !rdt_get_mon_l3_config(r); + return !rdt_get_mon_l3_config(r, mon_configurable); } =20 static __init void __check_quirks_intel(void) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index c049a274383c..45923eb4022f 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -72,11 +72,15 @@ DECLARE_STATIC_KEY_FALSE(rdt_mon_enable_key); * struct mon_evt - Entry in the event list of a resource * @evtid: event id * @name: name of the event + * @configurable: true if the event is configurable + * @config_name: sysfs file name of the event if configurable * @list: entry in &rdt_resource->evt_list */ struct mon_evt { u32 evtid; char *name; + bool configurable; + char *config_name; struct list_head list; }; =20 @@ -529,7 +533,7 @@ int closids_supported(void); void closid_free(int closid); int alloc_rmid(void); void free_rmid(u32 rmid); -int rdt_get_mon_l3_config(struct rdt_resource *r); +int rdt_get_mon_l3_config(struct rdt_resource *r, bool configurable); void mon_event_count(void *info); int rdtgroup_mondata_show(struct seq_file *m, void *arg); void rmdir_mondata_subdir_allrdtgrp(struct rdt_resource *r, diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index eaf25a234ff5..dc97aa7a3b3d 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -656,11 +656,13 @@ static struct mon_evt llc_occupancy_event =3D { static struct mon_evt mbm_total_event =3D { .name =3D "mbm_total_bytes", .evtid =3D QOS_L3_MBM_TOTAL_EVENT_ID, + .config_name =3D "mbm_total_config", }; =20 static struct mon_evt mbm_local_event =3D { .name =3D "mbm_local_bytes", .evtid =3D QOS_L3_MBM_LOCAL_EVENT_ID, + .config_name =3D "mbm_local_config", }; =20 /* @@ -682,7 +684,7 @@ static void l3_mon_evt_init(struct rdt_resource *r) list_add_tail(&mbm_local_event.list, &r->evt_list); } =20 -int rdt_get_mon_l3_config(struct rdt_resource *r) +int rdt_get_mon_l3_config(struct rdt_resource *r, bool configurable) { unsigned int mbm_offset =3D boot_cpu_data.x86_cache_mbm_width_offset; struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r); @@ -714,6 +716,11 @@ int rdt_get_mon_l3_config(struct rdt_resource *r) if (ret) return ret; =20 + if (configurable) { + mbm_total_event.configurable =3D true; + mbm_local_event.configurable =3D true; + } + l3_mon_evt_init(r); =20 r->mon_capable =3D true; diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index fc5286067201..f55a693fa958 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1001,8 +1001,11 @@ static int rdt_mon_features_show(struct kernfs_open_= file *of, struct rdt_resource *r =3D of->kn->parent->priv; struct mon_evt *mevt; =20 - list_for_each_entry(mevt, &r->evt_list, list) + list_for_each_entry(mevt, &r->evt_list, list) { seq_printf(seq, "%s\n", mevt->name); + if (mevt->configurable) + seq_printf(seq, "%s\n", mevt->config_name); + } =20 return 0; } From nobody Fri Apr 10 15:42:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8AD40C38145 for ; Wed, 7 Sep 2022 18:02:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230292AbiIGSCG (ORCPT ); Wed, 7 Sep 2022 14:02:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230267AbiIGSBg (ORCPT ); Wed, 7 Sep 2022 14:01:36 -0400 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2067.outbound.protection.outlook.com [40.107.237.67]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD889C00ED; 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Wed, 7 Sep 2022 18:01:10 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT116.mail.protection.outlook.com (10.13.176.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5612.13 via Frontend Transport; Wed, 7 Sep 2022 18:01:10 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Wed, 7 Sep 2022 13:01:02 -0500 Subject: [PATCH v4 09/13] x86/resctrl: Add sysfs interface files to read/write event configuration From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Wed, 7 Sep 2022 13:01:02 -0500 Message-ID: <166257366204.1043018.4834615270384002210.stgit@bmoger-ubuntu> In-Reply-To: <166257348081.1043018.11227924488792315932.stgit@bmoger-ubuntu> References: <166257348081.1043018.11227924488792315932.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Sep 2022 18:01:10.2723 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 954dced1-085e-4b9c-8de2-08da90faf20a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT116.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB4881 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add two new sysfs files to read/write the event configuration if the feature Bandwidth Monitoring Event Configuration (BMEC) is supported. The file mbm_local_config is for the configuration of the event mbm_local_bytes and the file mbm_total_config is for the configuration of mbm_total_bytes. $ls /sys/fs/resctrl/mon_data/mon_L3_00/mbm_local* /sys/fs/resctrl/mon_data/mon_L3_00/mbm_local_bytes /sys/fs/resctrl/mon_data/mon_L3_00/mbm_local_config $ls /sys/fs/resctrl/mon_data/mon_L3_00/mbm_total* /sys/fs/resctrl/mon_data/mon_L3_00/mbm_total_bytes /sys/fs/resctrl/mon_data/mon_L3_00/mbm_total_config Signed-off-by: Babu Moger --- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 40 ++++++++++++++++++++++++----= ---- 1 file changed, 30 insertions(+), 10 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index f55a693fa958..da11fdad204d 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -254,6 +254,10 @@ static const struct kernfs_ops kf_mondata_ops =3D { .seq_show =3D rdtgroup_mondata_show, }; =20 +static const struct kernfs_ops kf_mondata_config_ops =3D { + .atomic_write_len =3D PAGE_SIZE, +}; + static bool is_cpu_list(struct kernfs_open_file *of) { struct rftype *rft =3D of->kn->priv; @@ -2478,24 +2482,40 @@ static struct file_system_type rdt_fs_type =3D { .kill_sb =3D rdt_kill_sb, }; =20 -static int mon_addfile(struct kernfs_node *parent_kn, const char *name, +static int mon_addfile(struct kernfs_node *parent_kn, struct mon_evt *mevt, void *priv) { - struct kernfs_node *kn; + struct kernfs_node *kn_evt, *kn_evt_config; int ret =3D 0; =20 - kn =3D __kernfs_create_file(parent_kn, name, 0444, - GLOBAL_ROOT_UID, GLOBAL_ROOT_GID, 0, - &kf_mondata_ops, priv, NULL, NULL); - if (IS_ERR(kn)) - return PTR_ERR(kn); + kn_evt =3D __kernfs_create_file(parent_kn, mevt->name, 0444, + GLOBAL_ROOT_UID, GLOBAL_ROOT_GID, 0, + &kf_mondata_ops, priv, NULL, NULL); + if (IS_ERR(kn_evt)) + return PTR_ERR(kn_evt); =20 - ret =3D rdtgroup_kn_set_ugid(kn); + ret =3D rdtgroup_kn_set_ugid(kn_evt); if (ret) { - kernfs_remove(kn); + kernfs_remove(kn_evt); return ret; } =20 + if (mevt->configurable) { + kn_evt_config =3D __kernfs_create_file(parent_kn, + mevt->config_name, 0644, + GLOBAL_ROOT_UID, GLOBAL_ROOT_GID, 0, + &kf_mondata_config_ops, priv, NULL, NULL); + if (IS_ERR(kn_evt_config)) + return PTR_ERR(kn_evt_config); + + ret =3D rdtgroup_kn_set_ugid(kn_evt_config); + if (ret) { + kernfs_remove(kn_evt_config); + kernfs_remove(kn_evt); + return ret; + } + } + return ret; } =20 @@ -2550,7 +2570,7 @@ static int mkdir_mondata_subdir(struct kernfs_node *p= arent_kn, priv.u.domid =3D d->id; list_for_each_entry(mevt, &r->evt_list, list) { priv.u.evtid =3D mevt->evtid; - ret =3D mon_addfile(kn, mevt->name, priv.priv); + ret =3D mon_addfile(kn, mevt, priv.priv); if (ret) goto out_destroy; =20 From nobody Fri Apr 10 15:42:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 106C8C38145 for ; Wed, 7 Sep 2022 18:02:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230376AbiIGSCX (ORCPT ); Wed, 7 Sep 2022 14:02:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50754 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229830AbiIGSBq (ORCPT ); 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Wed, 7 Sep 2022 13:01:09 -0500 Subject: [PATCH v4 10/13] x86/resctrl: Add the sysfs interface to read the event configuration From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Wed, 7 Sep 2022 13:01:09 -0500 Message-ID: <166257366902.1043018.16087054015308149859.stgit@bmoger-ubuntu> In-Reply-To: <166257348081.1043018.11227924488792315932.stgit@bmoger-ubuntu> References: <166257348081.1043018.11227924488792315932.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT116:EE_|BL3PR12MB6473:EE_ X-MS-Office365-Filtering-Correlation-Id: 19499cc3-e96c-4921-e4ab-08da90faf2c6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Sep 2022 18:01:11.4909 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 19499cc3-e96c-4921-e4ab-08da90faf2c6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT116.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6473 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The current event configuration can be viewed by the user by reading the sysfs configuration file. Following are the types of events supported: =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Bits Description =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D 6 Dirty Victims from the QOS domain to all types of memory 5 Reads to slow memory in the non-local NUMA domain 4 Reads to slow memory in the local NUMA domain 3 Non-temporal writes to non-local NUMA domain 2 Non-temporal writes to local NUMA domain 1 Reads to memory in the non-local NUMA domain 0 Reads to memory in the local NUMA domain =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D By default, the mbm_total_bytes configuration is set to 0x7F to count all the event types and the mbm_local_bytes configuration is set to 0x15 to count all the local memory events. $cat /sys/fs/resctrl/mon_data/mon_L3_00/mbm_total_config 0x7f $cat /sys/fs/resctrl/mon_data/mon_L3_00/mbm_local_config 0x15 Signed-off-by: Babu Moger --- arch/x86/kernel/cpu/resctrl/internal.h | 24 ++++++++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 77 ++++++++++++++++++++++++++++= ++++ 2 files changed, 101 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 45923eb4022f..96f439324d78 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -15,6 +15,7 @@ #define MSR_IA32_MBA_THRTL_BASE 0xd50 #define MSR_IA32_MBA_BW_BASE 0xc0000200 #define MSR_IA32_SMBA_BW_BASE 0xc0000280 +#define MSR_IA32_EVT_CFG_BASE 0xc0000400 =20 #define MSR_IA32_QM_CTR 0x0c8e #define MSR_IA32_QM_EVTSEL 0x0c8d @@ -50,6 +51,29 @@ */ #define MBM_CNTR_WIDTH_OFFSET_MAX (62 - MBM_CNTR_WIDTH_BASE) =20 +/* Reads to Local DRAM Memory */ +#define READS_TO_LOCAL_MEM BIT(0) + +/* Reads to Remote DRAM Memory */ +#define READS_TO_REMOTE_MEM BIT(1) + +/* Non-Temporal Writes to Local Memory */ +#define NON_TEMP_WRITE_TO_LOCAL_MEM BIT(2) + +/* Non-Temporal Writes to Remote Memory */ +#define NON_TEMP_WRITE_TO_REMOTE_MEM BIT(3) + +/* Reads to Local Memory the system identifies as "Slow Memory" */ +#define READS_TO_LOCAL_S_MEM BIT(4) + +/* Reads to Remote Memory the system identifies as "Slow Memory" */ +#define READS_TO_REMOTE_S_MEM BIT(5) + +/* Dirty Victims to All Types of Memory */ +#define DIRTY_VICTIMS_TO_ALL_MEM BIT(6) + +/* Max event bits supported */ +#define MAX_EVT_CONFIG_BITS GENMASK(6, 0) =20 struct rdt_fs_context { struct kernfs_fs_context kfc; diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index da11fdad204d..6f067c1ac7c1 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -254,8 +254,85 @@ static const struct kernfs_ops kf_mondata_ops =3D { .seq_show =3D rdtgroup_mondata_show, }; =20 +struct mon_config_info { + u32 evtid; + u32 mon_config; +}; + +/* + * This is called via IPI to read the CQM/MBM counters + * in a domain. + */ +void mon_event_config_read(void *info) +{ + struct mon_config_info *mon_info =3D info; + u32 h, msr_index; + + switch (mon_info->evtid) { + case QOS_L3_MBM_TOTAL_EVENT_ID: + msr_index =3D 0; + break; + case QOS_L3_MBM_LOCAL_EVENT_ID: + msr_index =3D 1; + break; + default: + /* Not expected to come here */ + return; + } + + rdmsr(MSR_IA32_EVT_CFG_BASE + msr_index, mon_info->mon_config, h); +} + +void mondata_config_read(struct rdt_domain *d, struct mon_config_info *mon= _info) +{ + smp_call_function_any(&d->cpu_mask, mon_event_config_read, mon_info, 1); +} + +int rdtgroup_mondata_config_show(struct seq_file *m, void *arg) +{ + struct kernfs_open_file *of =3D m->private; + struct mon_config_info mon_info; + struct rdt_hw_resource *hw_res; + u32 resid, evtid, domid; + struct rdtgroup *rdtgrp; + struct rdt_resource *r; + union mon_data_bits md; + struct rdt_domain *d; + int ret =3D 0; + + rdtgrp =3D rdtgroup_kn_lock_live(of->kn); + if (!rdtgrp) { + ret =3D -ENOENT; + goto out; + } + + md.priv =3D of->kn->priv; + resid =3D md.u.rid; + domid =3D md.u.domid; + evtid =3D md.u.evtid; + + hw_res =3D &rdt_resources_all[resid]; + r =3D &hw_res->r_resctrl; + + d =3D rdt_find_domain(r, domid, NULL); + if (IS_ERR_OR_NULL(d)) { + ret =3D -ENOENT; + goto out; + } + + mon_info.evtid =3D evtid; + mondata_config_read(d, &mon_info); + + seq_printf(m, "0x%x\n", mon_info.mon_config); + +out: + rdtgroup_kn_unlock(of->kn); + return ret; +} + static const struct kernfs_ops kf_mondata_config_ops =3D { .atomic_write_len =3D PAGE_SIZE, + .seq_show =3D rdtgroup_mondata_config_show, }; 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Wed, 7 Sep 2022 18:01:27 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT038.mail.protection.outlook.com (10.13.176.246) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5612.13 via Frontend Transport; Wed, 7 Sep 2022 18:01:26 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Wed, 7 Sep 2022 13:01:16 -0500 Subject: [PATCH v4 11/13] x86/resctrl: Add sysfs interface to write the event configuration From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Wed, 7 Sep 2022 13:01:16 -0500 Message-ID: <166257367603.1043018.15774268739007323339.stgit@bmoger-ubuntu> In-Reply-To: <166257348081.1043018.11227924488792315932.stgit@bmoger-ubuntu> References: <166257348081.1043018.11227924488792315932.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Sep 2022 18:01:26.8492 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 039ec870-ccf1-49e7-ff3c-08da90fafbeb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT038.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4301 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the sysfs interface to write the event configuration for the MBM configurable events. The event configuration can be changed by writing to the sysfs file for that specific event. Following are the types of events supported: =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Bits Description =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D 6 Dirty Victims from the QOS domain to all types of memory 5 Reads to slow memory in the non-local NUMA domain 4 Reads to slow memory in the local NUMA domain 3 Non-temporal writes to non-local NUMA domain 2 Non-temporal writes to local NUMA domain 1 Reads to memory in the non-local NUMA domain 0 Reads to memory in the local NUMA domain =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D By default, the mbm_total_bytes configuration is set to 0x7F to count all the event types and the mbm_local_bytes configuration is set to 0x15 to count all the local memory events. For example: To change the mbm_total_bytes to count all the reads, run the command. $echo 0x33 > /sys/fs/resctrl/mon_data/mon_L3_00/mbm_total_config To change the mbm_local_bytes to count all the slow memory reads, run the command. $echo 0x30 > /sys/fs/resctrl/mon_data/mon_L3_00/mbm_local_config Signed-off-by: Babu Moger --- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 112 ++++++++++++++++++++++++++++= ++++ 1 file changed, 112 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 6f067c1ac7c1..59b484eb1267 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -330,9 +330,121 @@ int rdtgroup_mondata_config_show(struct seq_file *m, = void *arg) return ret; } =20 +/* + * This is called via IPI to read the CQM/MBM counters + * in a domain. + */ +void mon_event_config_write(void *info) +{ + struct mon_config_info *mon_info =3D info; + u32 msr_index; + + switch (mon_info->evtid) { + case QOS_L3_MBM_TOTAL_EVENT_ID: + msr_index =3D 0; + break; + case QOS_L3_MBM_LOCAL_EVENT_ID: + msr_index =3D 1; + break; + default: + /* Not expected to come here */ + return; + } + + wrmsr(MSR_IA32_EVT_CFG_BASE + msr_index, mon_info->mon_config, 0); +} + +ssize_t rdtgroup_mondata_config_write(struct kernfs_open_file *of, + char *buf, size_t nbytes, loff_t off) +{ + struct mon_config_info mon_info; + struct rdt_hw_resource *hw_res; + struct rdtgroup *rdtgrp; + struct rdt_resource *r; + unsigned int mon_config; + cpumask_var_t cpu_mask; + union mon_data_bits md; + struct rdt_domain *d; + u32 resid, domid; + int ret =3D 0, cpu; + + ret =3D kstrtouint(buf, 0, &mon_config); + if (ret) + return ret; + + rdt_last_cmd_clear(); + + /* mon_config cannot be more than the supported set of events */ + if (mon_config > MAX_EVT_CONFIG_BITS) { + rdt_last_cmd_puts("Invalid event configuration\n"); + return -EINVAL; + } + + cpus_read_lock(); + rdtgrp =3D rdtgroup_kn_lock_live(of->kn); + if (!rdtgrp) { + return -ENOENT; + goto e_unlock; + } + + if (!zalloc_cpumask_var(&cpu_mask, GFP_KERNEL)) { + ret =3D -ENOMEM; + goto e_unlock; + } + + md.priv =3D of->kn->priv; + resid =3D md.u.rid; + domid =3D md.u.domid; + + hw_res =3D &rdt_resources_all[resid]; + r =3D &hw_res->r_resctrl; + d =3D rdt_find_domain(r, domid, NULL); + if (IS_ERR_OR_NULL(d)) { + ret =3D -ENOENT; + goto e_cpumask; + } + + /* + * Read the current config value first. If both are same + * then we dont need to write again + */ + mon_info.evtid =3D md.u.evtid; + mondata_config_read(d, &mon_info); + if (mon_info.mon_config =3D=3D mon_config) + goto e_cpumask; + + mon_info.mon_config =3D mon_config; + + /* Pick all the CPUs in the domain instance */ + for_each_cpu(cpu, &d->cpu_mask) + cpumask_set_cpu(cpu, cpu_mask); + + /* Update MSR_IA32_EVT_CFG_BASE MSR on all the CPUs in cpu_mask */ + on_each_cpu_mask(cpu_mask, mon_event_config_write, &mon_info, 1); + + /* + * When an Event Configuration is changed, the bandwidth counters + * for all RMIDs and Events will be cleared, and the U-bit for every + * RMID will be set on the next read to any BwEvent for every RMID. + * Clear the mbm_local and mbm_total counts for all the RMIDs. + */ + memset(d->mbm_local, 0, sizeof(struct mbm_state) * r->num_rmid); + memset(d->mbm_total, 0, sizeof(struct mbm_state) * r->num_rmid); + +e_cpumask: + free_cpumask_var(cpu_mask); + +e_unlock: + rdtgroup_kn_unlock(of->kn); + cpus_read_unlock(); + + return ret ?: nbytes; +} + static const struct kernfs_ops kf_mondata_config_ops =3D { .atomic_write_len =3D PAGE_SIZE, .seq_show =3D rdtgroup_mondata_config_show, + .write =3D rdtgroup_mondata_config_write, }; =20 static bool is_cpu_list(struct kernfs_open_file *of) From nobody Fri Apr 10 15:42:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06532C54EE9 for ; Wed, 7 Sep 2022 18:02:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230392AbiIGSCn (ORCPT ); Wed, 7 Sep 2022 14:02:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51126 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230364AbiIGSCD (ORCPT ); Wed, 7 Sep 2022 14:02:03 -0400 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2072.outbound.protection.outlook.com [40.107.94.72]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 54A90BFE83; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Sep 2022 18:01:27.2554 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9e8e1706-289d-4462-fb2a-08da90fafc29 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT038.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6409 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The call on_each_cpu_mask can run the function on each CPU specified by cpumask, which may include the local processor. So, replace the call smp_call_function_many with on_each_cpu_mask to simplify the code. Signed-off-by: Babu Moger --- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 29 ++++++++--------------------- 1 file changed, 8 insertions(+), 21 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 59b484eb1267..fa0e1e8e29aa 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -518,12 +518,7 @@ static void update_cpu_closid_rmid(void *info) static void update_closid_rmid(const struct cpumask *cpu_mask, struct rdtgroup *r) { - int cpu =3D get_cpu(); - - if (cpumask_test_cpu(cpu, cpu_mask)) - update_cpu_closid_rmid(r); - smp_call_function_many(cpu_mask, update_cpu_closid_rmid, r, 1); - put_cpu(); + on_each_cpu_mask(cpu_mask, update_cpu_closid_rmid, r, 1); } =20 static int cpus_mon_write(struct rdtgroup *rdtgrp, cpumask_var_t newmask, @@ -2058,13 +2053,9 @@ static int set_cache_qos_cfg(int level, bool enable) /* Pick one CPU from each domain instance to update MSR */ cpumask_set_cpu(cpumask_any(&d->cpu_mask), cpu_mask); } - cpu =3D get_cpu(); - /* Update QOS_CFG MSR on this cpu if it's in cpu_mask. */ - if (cpumask_test_cpu(cpu, cpu_mask)) - update(&enable); - /* Update QOS_CFG MSR on all other cpus in cpu_mask. */ - smp_call_function_many(cpu_mask, update, &enable, 1); - put_cpu(); + + /* Update QOS_CFG MSR on all the CPUs in cpu_mask */ + on_each_cpu_mask(cpu_mask, update, &enable, 1); =20 free_cpumask_var(cpu_mask); =20 @@ -2506,7 +2497,7 @@ static int reset_all_ctrls(struct rdt_resource *r) struct msr_param msr_param; cpumask_var_t cpu_mask; struct rdt_domain *d; - int i, cpu; + int i; =20 if (!zalloc_cpumask_var(&cpu_mask, GFP_KERNEL)) return -ENOMEM; @@ -2527,13 +2518,9 @@ static int reset_all_ctrls(struct rdt_resource *r) for (i =3D 0; i < hw_res->num_closid; i++) hw_dom->ctrl_val[i] =3D r->default_ctrl; } - cpu =3D get_cpu(); - /* Update CBM on this cpu if it's in cpu_mask. */ - if (cpumask_test_cpu(cpu, cpu_mask)) - rdt_ctrl_update(&msr_param); - /* Update CBM on all other cpus in cpu_mask. */ - smp_call_function_many(cpu_mask, rdt_ctrl_update, &msr_param, 1); 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Wed, 7 Sep 2022 18:02:07 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000B8EE.mail.protection.outlook.com (10.167.241.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5612.9 via Frontend Transport; Wed, 7 Sep 2022 18:02:06 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Wed, 7 Sep 2022 13:01:30 -0500 Subject: [PATCH v4 13/13] Documentation/x86: Update resctrl_ui.rst for new features From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Wed, 7 Sep 2022 13:01:29 -0500 Message-ID: <166257368995.1043018.8665350782054895088.stgit@bmoger-ubuntu> In-Reply-To: <166257348081.1043018.11227924488792315932.stgit@bmoger-ubuntu> References: <166257348081.1043018.11227924488792315932.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Sep 2022 18:02:06.3202 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: addbbdd5-cef2-4e17-ff3d-08da90fb13ca X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000B8EE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5176 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Update the documentation for the new features: 1. Slow Memory Bandwidth allocation (SMBA). With this feature, the QOS enforcement policies can be applied to the external slow memory connected to the host. QOS enforcement is accomplished by assigning a Class Of Service (COS) to a processor and specifying allocations or limits for that COS for each resource to be allocated. 2. Bandwidth Monitoring Event Configuration (BMEC). The bandwidth monitoring events mbm_total_bytes and mbm_local_bytes are set to count all the total and local reads/writes respectively. With the introduction of slow memory, the two counters are not enough to count all the different types are memory events. With the feature BMEC, the users have the option to configure mbm_total_bytes and mbm_local_bytes to count the specific type of events. Also add configuration instructions with examples. Signed-off-by: Babu Moger --- Documentation/x86/resctrl.rst | 148 +++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 146 insertions(+), 2 deletions(-) diff --git a/Documentation/x86/resctrl.rst b/Documentation/x86/resctrl.rst index 71a531061e4e..56581587c1a3 100644 --- a/Documentation/x86/resctrl.rst +++ b/Documentation/x86/resctrl.rst @@ -17,14 +17,16 @@ AMD refers to this feature as AMD Platform Quality of S= ervice(AMD QoS). This feature is enabled by the CONFIG_X86_CPU_RESCTRL and the x86 /proc/cp= uinfo flag bits: =20 -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D RDT (Resource Director Technology) Allocation "rdt_a" CAT (Cache Allocation Technology) "cat_l3", "cat_l2" CDP (Code and Data Prioritization) "cdp_l3", "cdp_l2" CQM (Cache QoS Monitoring) "cqm_llc", "cqm_occup_llc" MBM (Memory Bandwidth Monitoring) "cqm_mbm_total", "cqm_mbm_local" MBA (Memory Bandwidth Allocation) "mba" -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +SMBA (Slow Memory Bandwidth Allocation) "smba" +BMEC (Bandwidth Monitoring Event Configuration) "bmec" +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D =20 To use the feature mount the file system:: =20 @@ -161,6 +163,23 @@ with the following files: "mon_features": Lists the monitoring events if monitoring is enabled for the resource. + Example output: + + # cat /sys/fs/resctrl/info/L3_MON/mon_features + llc_occupancy + mbm_total_bytes + mbm_local_bytes + + If the system supports Bandwidth Monitoring Event + Configuration (BMEC), then the bandwidth events will + be configurable. Then the output will be. + + # cat /sys/fs/resctrl/info/L3_MON/mon_features + llc_occupancy + mbm_total_bytes + mbm_total_config + mbm_local_bytes + mbm_local_config =20 "max_threshold_occupancy": Read/write file provides the largest value (in @@ -264,6 +283,32 @@ When monitoring is enabled all MON groups will also co= ntain: the sum for all tasks in the CTRL_MON group and all tasks in MON groups. Please see example section for more details on usage. =20 +"mbm_total_config", "mbm_local_config": + This contains the current event configuration for the events + mbm_total_bytes and mbm_local_bytes, respectively, when the + Bandwidth Monitoring Event Configuration (BMEC) feature is support= ed. + These files are organized by L3 domains under the subdirectories + "mon_L3_00" and "mon_L3_01". When BMEC is supported, the events + mbm_local_bytes and mbm_total_bytes are configurable. + + Following are the types of events supported: + + =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + Bits Description + =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + 6 Dirty Victims from the QOS domain to all types of memory + 5 Reads to slow memory in the non-local NUMA domain + 4 Reads to slow memory in the local NUMA domain + 3 Non-temporal writes to non-local NUMA domain + 2 Non-temporal writes to local NUMA domain + 1 Reads to memory in the non-local NUMA domain + 0 Reads to memory in the local NUMA domain + =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + + By default, the mbm_total_bytes configuration is set to 0x7F to co= unt + all the event types and the mbm_local_bytes configuration is set to + 0x15 to count all the local memory events. + Resource allocation rules ------------------------- =20 @@ -464,6 +509,19 @@ Memory bandwidth domain is L3 cache. =20 MB:=3Dbw_MBps0;=3Dbw_MBps1;... =20 +Slow Memory bandwidth Allocation (when supported) +------------------------------------------------- +Currently, CXL.memory is the only supported "slow" memory device. +With the support of SMBA feature the hardware enables bandwidth +allocation on the slow memory devices. If there are multiple slow +memory devices in the system, then the throttling logic groups all +the slow sources together and applies the limit on them as a whole. + +Slow Memory b/w domain is L3 cache. +:: + + SMBA:=3Dbandwidth0;=3Dbandwidth1;... + Reading/writing the schemata file --------------------------------- Reading the schemata file will show the state of all resources @@ -479,6 +537,44 @@ which you wish to change. E.g. L3DATA:0=3Dfffff;1=3Dfffff;2=3D3c0;3=3Dfffff L3CODE:0=3Dfffff;1=3Dfffff;2=3Dfffff;3=3Dfffff =20 +Reading/writing the schemata file (on AMD systems) +-------------------------------------------------- +Reading the schemata file will show the state of all resources +on all domains. When writing the memory bandwidth allocation you +only need to specify those values in an absolute number expressed +in 1/8 GB/s increments. To allocate bandwidth limit of 2GB, you +need to specify the value 16 (16 * 1/8 =3D 2). E.g. +:: + + # cat schemata + MB:0=3D2048;1=3D2048;2=3D2048;3=3D2048 + L3:0=3Dffff;1=3Dffff;2=3Dffff;3=3Dffff + + # echo "MB:1=3D16" > schemata + # cat schemata + MB:0=3D2048;1=3D 16;2=3D2048;3=3D2048 + L3:0=3Dffff;1=3Dffff;2=3Dffff;3=3Dffff + +Reading/writing the schemata file (on AMD systems) with slow memory +------------------------------------------------------------------- +Reading the schemata file will show the state of all resources +on all domains. When writing the memory bandwidth allocation you +only need to specify those values in an absolute number expressed +in 1/8 GB/s increments. To allocate bandwidth limit of 8GB, you +need to specify the value 64 (64 * 1/8 =3D 8). E.g. +:: + + # cat schemata + SMBA:0=3D2048;1=3D2048;2=3D2048;3=3D2048 + MB:0=3D2048;1=3D2048;2=3D2048;3=3D2048 + L3:0=3Dffff;1=3Dffff;2=3Dffff;3=3Dffff + + # echo "SMBA:1=3D64" > schemata + # cat schemata + SMBA:0=3D2048;1=3D 64;2=3D2048;3=3D2048 + MB:0=3D2048;1=3D2048;2=3D2048;3=3D2048 + L3:0=3Dffff;1=3Dffff;2=3Dffff;3=3Dffff + Cache Pseudo-Locking =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D CAT enables a user to specify the amount of cache space that an @@ -1210,6 +1306,54 @@ View the llc occupancy snapshot:: # cat /sys/fs/resctrl/p1/mon_data/mon_L3_00/llc_occupancy 11234000 =20 +Example 5 (Configure and Monitor specific event types) +------------------------------------------------------ + +A single socket system which has real time tasks running on cores 0-4 +and non real time tasks on other CPUs. We want to monitor the memory +bandwidth allocation for specific events. +:: + + # mount -t resctrl resctrl /sys/fs/resctrl + # cd /sys/fs/resctrl + # mkdir p1 + +Move the CPUs 0-4 over to p1:: + + # echo 0xf > p1/cpus + +View the current mbm_local_bytes:: + + # cat /sys/fs/resctrl/p1/mon_data/mon_L3_00/mbm_local_bytes + 112501 + +Change the mbm_local_bytes to count mon-temporal writes to both local +and non-local NUMA domain. Refer to event supported bitmap under +mbm_local_config:: + + # echo 0xc > /sys/fs/resctrl/p1/mon_data/mon_L3_00/mbm_local_config + +View the updated mbm_local_bytes:: + + # cat /sys/fs/resctrl/p1/mon_data/mon_L3_00/mbm_local_bytes + 12601 + +Similar experiment on mbm_total_bytes. First view the current mbm_total_by= tes:: + + # cat /sys/fs/resctrl/p1/mon_data/mon_L3_00/mbm_total_bytes + 1532501 + +Change the mbm_total_bytes to count only reads to slow memory on both local +and non-local NUMA domain. Refer to event supported bitmap under +mbm_total_config:: + + # echo 0x30 > /sys/fs/resctrl/p1/mon_data/mon_L3_00/mbm_total_config + +View the updated mbm_total_bytes:: + + # cat /sys/fs/resctrl/p1/mon_data/mon_L3_00/mbm_total_bytes + 104562 + Intel RDT Errata =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20