From nobody Mon Apr 6 15:40:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06760C38145 for ; Tue, 6 Sep 2022 09:42:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230248AbiIFJmJ (ORCPT ); Tue, 6 Sep 2022 05:42:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239357AbiIFJlj (ORCPT ); Tue, 6 Sep 2022 05:41:39 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1B3B47548F; Tue, 6 Sep 2022 02:41:38 -0700 (PDT) Date: Tue, 06 Sep 2022 09:41:35 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1662457296; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yk/M/Btz3UQ+D2dDlDmoWwKldQ/Q384INUORtAdcm10=; b=rS3oSWJG4A+hvFYJt+7De1/DH0VuIQPCskHtTPhabpXQ9YcU0BJNybbDh1pAxLAdgEKUnB oHKxgDeXv9o829GgibzjVzBZgoVm8qBZ7sbTwk6tYmNtTzsZWbSINYTf06Zdv3qn6kad99 XXlM6LmSPTXa7ONVSU6TMfFHLYEaE3op1CmW70d5rUogf3cmAb7/0RmhNA6Y40GfQlzpSN WQuApL6YGHyWTWeqeoj+2G9vgh4GqqWBI+2vpnJv9qVdvhD3c9XdUrLdWTecdOPbqhSxRb XJbpOAtUk+jYQhlUJMOjXCL0/FaNJ8QNmobeb384EgdLCCTk2jUXRKTeChFfGw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1662457296; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yk/M/Btz3UQ+D2dDlDmoWwKldQ/Q384INUORtAdcm10=; b=+RTQU6VB/fNDCUHScCx/qs0jS2OMGG4fuP9wp7cAUIBe0jAxs3zA5o7cQPrTSCem4le7Zo ce4JKt7ckeUvBBBw== From: "tip-bot2 for Yang Jihong" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/urgent] perf/core: Fix reentry problem in perf_output_read_group() Cc: Yang Jihong , "Peter Zijlstra (Intel)" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20220902082918.179248-1-yangjihong1@huawei.com> References: <20220902082918.179248-1-yangjihong1@huawei.com> MIME-Version: 1.0 Message-ID: <166245729557.401.10270808744010825515.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the perf/urgent branch of tip: Commit-ID: 6b959ba22d34ca793ffdb15b5715457c78e38b1a Gitweb: https://git.kernel.org/tip/6b959ba22d34ca793ffdb15b5715457c7= 8e38b1a Author: Yang Jihong AuthorDate: Fri, 02 Sep 2022 16:29:18 +08:00 Committer: Peter Zijlstra CommitterDate: Tue, 06 Sep 2022 11:33:00 +02:00 perf/core: Fix reentry problem in perf_output_read_group() perf_output_read_group may respond to IPI request of other cores and invoke __perf_install_in_context function. As a result, hwc configuration is modif= ied. causing inconsistency and unexpected consequences. Interrupts are not disabled when perf_output_read_group reads PMU counter. In this case, IPI request may be received from other cores. As a result, PMU configuration is modified and an error occurs when reading PMU counter: CPU0 CPU1 __se_sys_perf_event_open perf_install_in_context perf_output_read_group smp_call_function= _single for_each_sibling_event(sub, leader) { generic_exec_si= ngle if ((sub !=3D event) && remote_func= tion (sub->state =3D=3D PERF_EVENT_STATE_ACTIVE)) | <----RAISE IPI-----+ __perf_install_in_context ctx_resched event_sched_out armpmu_del ... hwc->idx =3D -1; // event->hwc.idx is set to -1 ... sub->pmu->read(sub); armpmu_read armv8pmu_read_counter armv8pmu_read_hw_counter int idx =3D event->hw.idx; // idx =3D -1 u64 val =3D armv8pmu_read_evcntr(idx); u32 counter =3D ARMV8_IDX_TO_COUNTER(idx); // invalid counter =3D 30 read_pmevcntrn(counter) // undefined instruction Signed-off-by: Yang Jihong Signed-off-by: Peter Zijlstra (Intel) Link: https://lkml.kernel.org/r/20220902082918.179248-1-yangjihong1@huawei.= com --- kernel/events/core.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/kernel/events/core.c b/kernel/events/core.c index 2621fd2..ff4bffc 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -6893,9 +6893,16 @@ static void perf_output_read_group(struct perf_outpu= t_handle *handle, { struct perf_event *leader =3D event->group_leader, *sub; u64 read_format =3D event->attr.read_format; + unsigned long flags; u64 values[6]; int n =3D 0; =20 + /* + * Disabling interrupts avoids all counter scheduling + * (context switches, timer based rotation and IPIs). + */ + local_irq_save(flags); + values[n++] =3D 1 + leader->nr_siblings; =20 if (read_format & PERF_FORMAT_TOTAL_TIME_ENABLED) @@ -6931,6 +6938,8 @@ static void perf_output_read_group(struct perf_output= _handle *handle, =20 __output_copy(handle, values, n * sizeof(u64)); } + + local_irq_restore(flags); } =20 #define PERF_FORMAT_TOTAL_TIMES (PERF_FORMAT_TOTAL_TIME_ENABLED|\