From nobody Tue Apr 7 10:40:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68010ECAAD2 for ; Mon, 29 Aug 2022 15:16:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229739AbiH2PQq (ORCPT ); Mon, 29 Aug 2022 11:16:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229680AbiH2PQo (ORCPT ); Mon, 29 Aug 2022 11:16:44 -0400 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 51C247A50E for ; Mon, 29 Aug 2022 08:16:43 -0700 (PDT) Received: from dude02.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::28]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1oSgUz-0006bl-1e; Mon, 29 Aug 2022 17:16:25 +0200 From: Lucas Stach To: Richard Zhu Cc: p.zabel@pengutronix.de, bhelgaas@google.com, lorenzo.pieralisi@arm.com, robh@kernel.org, shawnguo@kernel.org, vkoul@kernel.org, alexander.stein@ew.tq-group.com, marex@denx.de, richard.leitner@linux.dev, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com Subject: [PATCH 1/2] soc: imx: imx8mp-blk-ctrl: handle PCIe PHY resets Date: Mon, 29 Aug 2022 17:16:22 +0200 Message-Id: <20220829151623.808344-1-l.stach@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <1661760917-9558-1-git-send-email-hongxing.zhu@nxp.com> References: <1661760917-9558-1-git-send-email-hongxing.zhu@nxp.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::28 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Dessert the PHY reset when powering up the domain and put it back into reset when the domain is powered down. Signed-off-by: Lucas Stach --- drivers/soc/imx/imx8mp-blk-ctrl.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c b/drivers/soc/imx/imx8mp-blk= -ctrl.c index 4ca2ede6871b..6c939d68ba9a 100644 --- a/drivers/soc/imx/imx8mp-blk-ctrl.c +++ b/drivers/soc/imx/imx8mp-blk-ctrl.c @@ -18,6 +18,8 @@ #define GPR_REG0 0x0 #define PCIE_CLOCK_MODULE_EN BIT(0) #define USB_CLOCK_MODULE_EN BIT(1) +#define PCIE_PHY_APB_RST BIT(4) +#define PCIE_PHY_INIT_RST BIT(5) =20 struct imx8mp_blk_ctrl_domain; =20 @@ -75,6 +77,10 @@ static void imx8mp_hsio_blk_ctrl_power_on(struct imx8mp_= blk_ctrl *bc, case IMX8MP_HSIOBLK_PD_PCIE: regmap_set_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN); break; + case IMX8MP_HSIOBLK_PD_PCIE_PHY: + regmap_set_bits(bc->regmap, GPR_REG0, + PCIE_PHY_APB_RST | PCIE_PHY_INIT_RST); + break; default: break; } @@ -90,6 +96,10 @@ static void imx8mp_hsio_blk_ctrl_power_off(struct imx8mp= _blk_ctrl *bc, case IMX8MP_HSIOBLK_PD_PCIE: regmap_clear_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN); break; + case IMX8MP_HSIOBLK_PD_PCIE_PHY: + regmap_clear_bits(bc->regmap, GPR_REG0, + PCIE_PHY_APB_RST | PCIE_PHY_INIT_RST); + break; default: break; } --=20 2.30.2 From nobody Tue Apr 7 10:40:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D20CECAAD2 for ; Mon, 29 Aug 2022 08:33:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229959AbiH2IdK (ORCPT ); Mon, 29 Aug 2022 04:33:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35842 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229806AbiH2Ic5 (ORCPT ); Mon, 29 Aug 2022 04:32:57 -0400 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4EB60578AF; Mon, 29 Aug 2022 01:32:56 -0700 (PDT) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id A88B5200FC5; Mon, 29 Aug 2022 10:32:54 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 6DA95200FAC; Mon, 29 Aug 2022 10:32:54 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 672CA180031E; Mon, 29 Aug 2022 16:32:52 +0800 (+08) From: Richard Zhu To: p.zabel@pengutronix.de, l.stach@pengutronix.de, bhelgaas@google.com, lorenzo.pieralisi@arm.com, robh@kernel.org, shawnguo@kernel.org, vkoul@kernel.org, alexander.stein@ew.tq-group.com, marex@denx.de, richard.leitner@linux.dev Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com, Richard Zhu Subject: [PATCH v4 1/6] reset: imx7: Fix the iMX8MP PCIe PHY PERST support Date: Mon, 29 Aug 2022 16:15:12 +0800 Message-Id: <1661760917-9558-2-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1661760917-9558-1-git-send-email-hongxing.zhu@nxp.com> References: <1661760917-9558-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" On i.MX7/iMX8MM/iMX8MQ, the initialized default value of PERST bit(BIT3) of SRC_PCIEPHY_RCR is 1b'1. But i.MX8MP has one inversed default value 1b'0 of PERST bit. And the PERST bit should be kept 1b'1 after power and clocks are stable. So fix the i.MX8MP PCIe PHY PERST support here. Fixes: e08672c03981 ("reset: imx7: Add support for i.MX8MP SoC") Signed-off-by: Richard Zhu Reviewed-by: Philipp Zabel Tested-by: Marek Vasut Tested-by: Richard Leitner Tested-by: Alexander Stein --- drivers/reset/reset-imx7.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c index 185a333df66c..d2408725eb2c 100644 --- a/drivers/reset/reset-imx7.c +++ b/drivers/reset/reset-imx7.c @@ -329,6 +329,7 @@ static int imx8mp_reset_set(struct reset_controller_dev= *rcdev, break; =20 case IMX8MP_RESET_PCIE_CTRL_APPS_EN: + case IMX8MP_RESET_PCIEPHY_PERST: value =3D assert ? 0 : bit; break; } --=20 2.25.1 From nobody Tue Apr 7 10:40:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3945EECAAD2 for ; Mon, 29 Aug 2022 08:33:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229963AbiH2IdF (ORCPT ); Mon, 29 Aug 2022 04:33:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229819AbiH2Ic7 (ORCPT ); Mon, 29 Aug 2022 04:32:59 -0400 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 984AD578BC; Mon, 29 Aug 2022 01:32:57 -0700 (PDT) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 2534B1A0FCA; Mon, 29 Aug 2022 10:32:56 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id DD2E91A0FBF; Mon, 29 Aug 2022 10:32:55 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id E26011820F59; Mon, 29 Aug 2022 16:32:53 +0800 (+08) From: Richard Zhu To: p.zabel@pengutronix.de, l.stach@pengutronix.de, bhelgaas@google.com, lorenzo.pieralisi@arm.com, robh@kernel.org, shawnguo@kernel.org, vkoul@kernel.org, alexander.stein@ew.tq-group.com, marex@denx.de, richard.leitner@linux.dev Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com, Richard Zhu Subject: [PATCH v4 2/6] dt-binding: phy: Add iMX8MP PCIe PHY binding Date: Mon, 29 Aug 2022 16:15:13 +0800 Message-Id: <1661760917-9558-3-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1661760917-9558-1-git-send-email-hongxing.zhu@nxp.com> References: <1661760917-9558-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add i.MX8MP PCIe PHY binding. On iMX8MM, the initialized default value of PERST bit(BIT3) of SRC_PCIEPHY_RCR is 1b'1. But i.MX8MP has one inversed default value 1b'0 of PERST bit. And the PERST bit should be kept 1b'1 after power and clocks are stable. So add one more PERST explicitly for i.MX8MP PCIe PHY. Signed-off-by: Richard Zhu Tested-by: Marek Vasut Tested-by: Richard Leitner Tested-by: Alexander Stein --- .../bindings/phy/fsl,imx8-pcie-phy.yaml | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml b= /Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml index b6421eedece3..692783c7fd69 100644 --- a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml @@ -16,6 +16,7 @@ properties: compatible: enum: - fsl,imx8mm-pcie-phy + - fsl,imx8mp-pcie-phy =20 reg: maxItems: 1 @@ -28,11 +29,16 @@ properties: - const: ref =20 resets: - maxItems: 1 + minItems: 1 + maxItems: 2 =20 reset-names: - items: - - const: pciephy + oneOf: + - items: # for iMX8MM + - const: pciephy + - items: # for IMX8MP + - const: pciephy + - const: perst =20 fsl,refclk-pad-mode: description: | @@ -60,6 +66,10 @@ properties: description: A boolean property indicating the CLKREQ# signal is not supported in the board design (optional) =20 + power-domains: + description: PCIe PHY power domain (optional). + maxItems: 1 + required: - "#phy-cells" - compatible --=20 2.25.1 From nobody Tue Apr 7 10:40:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7ED18ECAAD4 for ; Mon, 29 Aug 2022 08:33:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230017AbiH2IdP (ORCPT ); Mon, 29 Aug 2022 04:33:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35968 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229862AbiH2IdC (ORCPT ); Mon, 29 Aug 2022 04:33:02 -0400 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8A660578A7; Mon, 29 Aug 2022 01:32:59 -0700 (PDT) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id C13B61A0FDA; Mon, 29 Aug 2022 10:32:57 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 6080B1A0FD9; Mon, 29 Aug 2022 10:32:57 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 60992180031E; Mon, 29 Aug 2022 16:32:55 +0800 (+08) From: Richard Zhu To: p.zabel@pengutronix.de, l.stach@pengutronix.de, bhelgaas@google.com, lorenzo.pieralisi@arm.com, robh@kernel.org, shawnguo@kernel.org, vkoul@kernel.org, alexander.stein@ew.tq-group.com, marex@denx.de, richard.leitner@linux.dev Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com, Richard Zhu Subject: [PATCH v4 3/6] phy: freescale: imx8m-pcie: Add iMX8MP PCIe PHY support Date: Mon, 29 Aug 2022 16:15:14 +0800 Message-Id: <1661760917-9558-4-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1661760917-9558-1-git-send-email-hongxing.zhu@nxp.com> References: <1661760917-9558-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add i.MX8MP PCIe PHY support Signed-off-by: Richard Zhu Tested-by: Marek Vasut Tested-by: Richard Leitner Tested-by: Alexander Stein --- drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 150 ++++++++++++++------- 1 file changed, 104 insertions(+), 46 deletions(-) diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/frees= cale/phy-fsl-imx8m-pcie.c index ad7d2edfc414..3463b4299f2f 100644 --- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c +++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c @@ -11,6 +11,8 @@ #include #include #include +#include +#include #include #include #include @@ -31,12 +33,10 @@ #define IMX8MM_PCIE_PHY_CMN_REG065 0x194 #define ANA_AUX_RX_TERM (BIT(7) | BIT(4)) #define ANA_AUX_TX_LVL GENMASK(3, 0) -#define IMX8MM_PCIE_PHY_CMN_REG75 0x1D4 -#define PCIE_PHY_CMN_REG75_PLL_DONE 0x3 +#define IMX8MM_PCIE_PHY_CMN_REG075 0x1D4 +#define ANA_PLL_DONE 0x3 #define PCIE_PHY_TRSV_REG5 0x414 -#define PCIE_PHY_TRSV_REG5_GEN1_DEEMP 0x2D #define PCIE_PHY_TRSV_REG6 0x418 -#define PCIE_PHY_TRSV_REG6_GEN2_DEEMP 0xF =20 #define IMX8MM_GPR_PCIE_REF_CLK_SEL GENMASK(25, 24) #define IMX8MM_GPR_PCIE_REF_CLK_PLL FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL= , 0x3) @@ -47,16 +47,29 @@ #define IMX8MM_GPR_PCIE_SSC_EN BIT(16) #define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE BIT(9) =20 +#define IMX8MP_GPR_REG0 0x0 +#define IMX8MP_GPR_PHY_APB_RST BIT(4) +#define IMX8MP_GPR_PHY_INIT_RST BIT(5) + +enum imx8_pcie_phy_type { + IMX8MM, + IMX8MP, +}; + struct imx8_pcie_phy { void __iomem *base; + struct device *dev; struct clk *clk; struct phy *phy; + struct regmap *hsio_blk_ctrl; struct regmap *iomuxc_gpr; struct reset_control *reset; + struct reset_control *perst; u32 refclk_pad_mode; u32 tx_deemph_gen1; u32 tx_deemph_gen2; bool clkreq_unused; + enum imx8_pcie_phy_type variant; }; =20 static int imx8_pcie_phy_init(struct phy *phy) @@ -68,31 +81,27 @@ static int imx8_pcie_phy_init(struct phy *phy) reset_control_assert(imx8_phy->reset); =20 pad_mode =3D imx8_phy->refclk_pad_mode; - /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */ - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, - IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE, - imx8_phy->clkreq_unused ? - 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE); - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, - IMX8MM_GPR_PCIE_AUX_EN, - IMX8MM_GPR_PCIE_AUX_EN); - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, - IMX8MM_GPR_PCIE_POWER_OFF, 0); - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, - IMX8MM_GPR_PCIE_SSC_EN, 0); - - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, - IMX8MM_GPR_PCIE_REF_CLK_SEL, - pad_mode =3D=3D IMX8_PCIE_REFCLK_PAD_INPUT ? - IMX8MM_GPR_PCIE_REF_CLK_EXT : - IMX8MM_GPR_PCIE_REF_CLK_PLL); - usleep_range(100, 200); - - /* Do the PHY common block reset */ - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, - IMX8MM_GPR_PCIE_CMN_RST, - IMX8MM_GPR_PCIE_CMN_RST); - usleep_range(200, 500); + switch (imx8_phy->variant) { + case IMX8MM: + /* Tune PHY de-emphasis setting to pass PCIe compliance. */ + if (imx8_phy->tx_deemph_gen1) + writel(imx8_phy->tx_deemph_gen1, + imx8_phy->base + PCIE_PHY_TRSV_REG5); + if (imx8_phy->tx_deemph_gen2) + writel(imx8_phy->tx_deemph_gen2, + imx8_phy->base + PCIE_PHY_TRSV_REG6); + break; + case IMX8MP: + reset_control_assert(imx8_phy->perst); + + /* release pcie_phy_apb_reset and pcie_phy_init_resetn */ + regmap_update_bits(imx8_phy->hsio_blk_ctrl, IMX8MP_GPR_REG0, + IMX8MP_GPR_PHY_APB_RST | + IMX8MP_GPR_PHY_INIT_RST, + IMX8MP_GPR_PHY_APB_RST | + IMX8MP_GPR_PHY_INIT_RST); + break; + } =20 if (pad_mode =3D=3D IMX8_PCIE_REFCLK_PAD_INPUT || pad_mode =3D=3D IMX8_PCIE_REFCLK_PAD_UNUSED) { @@ -120,20 +129,44 @@ static int imx8_pcie_phy_init(struct phy *phy) imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG065); } =20 - /* Tune PHY de-emphasis setting to pass PCIe compliance. */ - if (imx8_phy->tx_deemph_gen1) - writel(imx8_phy->tx_deemph_gen1, - imx8_phy->base + PCIE_PHY_TRSV_REG5); - if (imx8_phy->tx_deemph_gen2) - writel(imx8_phy->tx_deemph_gen2, - imx8_phy->base + PCIE_PHY_TRSV_REG6); + /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */ + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, + IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE, + imx8_phy->clkreq_unused ? + 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE); + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, + IMX8MM_GPR_PCIE_AUX_EN, + IMX8MM_GPR_PCIE_AUX_EN); + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, + IMX8MM_GPR_PCIE_POWER_OFF, 0); + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, + IMX8MM_GPR_PCIE_SSC_EN, 0); + + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, + IMX8MM_GPR_PCIE_REF_CLK_SEL, + pad_mode =3D=3D IMX8_PCIE_REFCLK_PAD_INPUT ? + IMX8MM_GPR_PCIE_REF_CLK_EXT : + IMX8MM_GPR_PCIE_REF_CLK_PLL); + usleep_range(100, 200); =20 - reset_control_deassert(imx8_phy->reset); + /* Do the PHY common block reset */ + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, + IMX8MM_GPR_PCIE_CMN_RST, + IMX8MM_GPR_PCIE_CMN_RST); + + switch (imx8_phy->variant) { + case IMX8MP: + reset_control_deassert(imx8_phy->perst); + fallthrough; + case IMX8MM: + reset_control_deassert(imx8_phy->reset); + usleep_range(200, 500); + break; + } =20 /* Polling to check the phy is ready or not. */ - ret =3D readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG75, - val, val =3D=3D PCIE_PHY_CMN_REG75_PLL_DONE, - 10, 20000); + ret =3D readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG075, + val, val =3D=3D ANA_PLL_DONE, 10, 20000); return ret; } =20 @@ -160,18 +193,33 @@ static const struct phy_ops imx8_pcie_phy_ops =3D { .owner =3D THIS_MODULE, }; =20 +static const struct of_device_id imx8_pcie_phy_of_match[] =3D { + {.compatible =3D "fsl,imx8mm-pcie-phy", .data =3D (void *)IMX8MM}, + {.compatible =3D "fsl,imx8mp-pcie-phy", .data =3D (void *)IMX8MP}, + { }, +}; +MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match); + static int imx8_pcie_phy_probe(struct platform_device *pdev) { struct phy_provider *phy_provider; struct device *dev =3D &pdev->dev; + const struct of_device_id *of_id; struct device_node *np =3D dev->of_node; struct imx8_pcie_phy *imx8_phy; struct resource *res; =20 + of_id =3D of_match_device(imx8_pcie_phy_of_match, dev); + if (!of_id) + return -EINVAL; + imx8_phy =3D devm_kzalloc(dev, sizeof(*imx8_phy), GFP_KERNEL); if (!imx8_phy) return -ENOMEM; =20 + imx8_phy->dev =3D dev; + imx8_phy->variant =3D (enum imx8_pcie_phy_type)of_id->data; + /* get PHY refclk pad mode */ of_property_read_u32(np, "fsl,refclk-pad-mode", &imx8_phy->refclk_pad_mode); @@ -208,6 +256,22 @@ static int imx8_pcie_phy_probe(struct platform_device = *pdev) dev_err(dev, "Failed to get PCIEPHY reset control\n"); return PTR_ERR(imx8_phy->reset); } + if (imx8_phy->variant =3D=3D IMX8MP) { + /* Grab HSIO MIX config register range */ + imx8_phy->hsio_blk_ctrl =3D + syscon_regmap_lookup_by_compatible("fsl,imx8mp-hsio-blk-ctrl"); + if (IS_ERR(imx8_phy->hsio_blk_ctrl)) { + dev_err(dev, "Unable to find HSIO MIX registers\n"); + return PTR_ERR(imx8_phy->hsio_blk_ctrl); + } + + imx8_phy->perst =3D + devm_reset_control_get_exclusive(dev, "perst"); + if (IS_ERR(imx8_phy->perst)) { + dev_err(dev, "Failed to get PCIE PHY PERST control\n"); + return PTR_ERR(imx8_phy->perst); + } + } =20 res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); imx8_phy->base =3D devm_ioremap_resource(dev, res); @@ -225,12 +289,6 @@ static int imx8_pcie_phy_probe(struct platform_device = *pdev) return PTR_ERR_OR_ZERO(phy_provider); } =20 -static const struct of_device_id imx8_pcie_phy_of_match[] =3D { - {.compatible =3D "fsl,imx8mm-pcie-phy",}, - { }, -}; -MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match); - static struct platform_driver imx8_pcie_phy_driver =3D { .probe =3D imx8_pcie_phy_probe, .driver =3D { --=20 2.25.1 From nobody Tue Apr 7 10:40:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A89EECAAD2 for ; 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Mon, 29 Aug 2022 16:32:56 +0800 (+08) From: Richard Zhu To: p.zabel@pengutronix.de, l.stach@pengutronix.de, bhelgaas@google.com, lorenzo.pieralisi@arm.com, robh@kernel.org, shawnguo@kernel.org, vkoul@kernel.org, alexander.stein@ew.tq-group.com, marex@denx.de, richard.leitner@linux.dev Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com, Richard Zhu Subject: [PATCH v4 4/6] arm64: dts: imx8mp: Add iMX8MP PCIe support Date: Mon, 29 Aug 2022 16:15:15 +0800 Message-Id: <1661760917-9558-5-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1661760917-9558-1-git-send-email-hongxing.zhu@nxp.com> References: <1661760917-9558-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add i.MX8MP PCIe support. Signed-off-by: Richard Zhu Tested-by: Marek Vasut Tested-by: Richard Leitner Tested-by: Alexander Stein --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 46 ++++++++++++++++++++++- 1 file changed, 45 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mp.dtsi index fe178b7d063c..d11f079fd1f3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -5,6 +5,7 @@ =20 #include #include +#include #include #include #include @@ -410,7 +411,8 @@ iomuxc: pinctrl@30330000 { }; =20 gpr: iomuxc-gpr@30340000 { - compatible =3D "fsl,imx8mp-iomuxc-gpr", "syscon"; + compatible =3D "fsl,imx8mp-iomuxc-gpr", + "fsl,imx6q-iomuxc-gpr", "syscon"; reg =3D <0x30340000 0x10000>; }; =20 @@ -1084,6 +1086,17 @@ media_blk_ctrl: blk-ctrl@32ec0000 { #power-domain-cells =3D <1>; }; =20 + pcie_phy: pcie-phy@32f00000 { + compatible =3D "fsl,imx8mp-pcie-phy"; + reg =3D <0x32f00000 0x10000>; + resets =3D <&src IMX8MP_RESET_PCIEPHY>, + <&src IMX8MP_RESET_PCIEPHY_PERST>; + reset-names =3D "pciephy", "perst"; + power-domains =3D <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>; + #phy-cells =3D <0>; + status =3D "disabled"; + }; + hsio_blk_ctrl: blk-ctrl@32f10000 { compatible =3D "fsl,imx8mp-hsio-blk-ctrl", "syscon"; reg =3D <0x32f10000 0x24>; @@ -1099,6 +1112,37 @@ hsio_blk_ctrl: blk-ctrl@32f10000 { }; }; =20 + pcie: pcie@33800000 { + compatible =3D "fsl,imx8mp-pcie"; + reg =3D <0x33800000 0x400000>, <0x1ff00000 0x80000>; + reg-names =3D "dbi", "config"; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + bus-range =3D <0x00 0xff>; + ranges =3D <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downs= tream I/O 64KB */ + <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchab= le memory */ + num-lanes =3D <1>; + num-viewport =3D <4>; + interrupts =3D ; + interrupt-names =3D "msi"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + fsl,max-link-speed =3D <3>; + linux,pci-domain =3D <0>; + power-domains =3D <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; + resets =3D <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names =3D "apps", "turnoff"; + phys =3D <&pcie_phy>; + phy-names =3D "pcie-phy"; + status =3D "disabled"; + }; + gpu3d: gpu@38000000 { compatible =3D "vivante,gc"; reg =3D <0x38000000 0x8000>; --=20 2.25.1 From nobody Tue Apr 7 10:40:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C580ECAAD2 for ; Mon, 29 Aug 2022 08:33:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230056AbiH2Idd (ORCPT ); Mon, 29 Aug 2022 04:33:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229995AbiH2IdJ (ORCPT ); Mon, 29 Aug 2022 04:33:09 -0400 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F667578BA; Mon, 29 Aug 2022 01:33:03 -0700 (PDT) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id DD2261A2C9C; Mon, 29 Aug 2022 10:33:00 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 4E65A1A2C60; Mon, 29 Aug 2022 10:33:00 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 5382A181D0C0; Mon, 29 Aug 2022 16:32:58 +0800 (+08) From: Richard Zhu To: p.zabel@pengutronix.de, l.stach@pengutronix.de, bhelgaas@google.com, lorenzo.pieralisi@arm.com, robh@kernel.org, shawnguo@kernel.org, vkoul@kernel.org, alexander.stein@ew.tq-group.com, marex@denx.de, richard.leitner@linux.dev Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com, Richard Zhu Subject: [PATCH v4 5/6] arm64: dts: imx8mp-evk: Add PCIe support Date: Mon, 29 Aug 2022 16:15:16 +0800 Message-Id: <1661760917-9558-6-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1661760917-9558-1-git-send-email-hongxing.zhu@nxp.com> References: <1661760917-9558-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add PCIe support on i.MX8MP EVK board. Signed-off-by: Richard Zhu Tested-by: Marek Vasut Tested-by: Richard Leitner Tested-by: Alexander Stein --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 53 ++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot= /dts/freescale/imx8mp-evk.dts index f6b017ab5f53..defc92a8bb60 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -5,6 +5,7 @@ =20 /dts-v1/; =20 +#include #include "imx8mp.dtsi" =20 / { @@ -33,6 +34,12 @@ memory@40000000 { <0x1 0x00000000 0 0xc0000000>; }; =20 + pcie0_refclk: pcie0-refclk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <100000000>; + }; + reg_can1_stby: regulator-can1-stby { compatible =3D "regulator-fixed"; regulator-name =3D "can1-stby"; @@ -55,6 +62,17 @@ reg_can2_stby: regulator-can2-stby { enable-active-high; }; =20 + reg_pcie0: regulator-pcie { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pcie0_reg>; + regulator-name =3D "MPCIE_3V3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&gpio2 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible =3D "regulator-fixed"; pinctrl-names =3D "default"; @@ -350,6 +368,28 @@ &i2c5 { */ }; =20 +&pcie_phy { + fsl,refclk-pad-mode =3D ; + clocks =3D <&pcie0_refclk>; + clock-names =3D "ref"; + status =3D "okay"; +}; + +&pcie{ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pcie0>; + reset-gpio =3D <&gpio2 7 GPIO_ACTIVE_LOW>; + clocks =3D <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_PCIE_ROOT>, + <&clk IMX8MP_CLK_HSIO_AXI>; + clock-names =3D "pcie", "pcie_aux", "pcie_bus"; + assigned-clocks =3D <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-rates =3D <10000000>; + assigned-clock-parents =3D <&clk IMX8MP_SYS_PLL2_50M>; + vpcie-supply =3D <®_pcie0>; + status =3D "okay"; +}; + &snvs_pwrkey { status =3D "okay"; }; @@ -502,6 +542,19 @@ MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2 >; }; =20 + pinctrl_pcie0: pcie0grp { + fsl,pins =3D < + MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61 /* open drain, pull up */ + MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41 + >; + }; + + pinctrl_pcie0_reg: pcie0reggrp { + fsl,pins =3D < + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41 + >; + }; + pinctrl_pmic: pmicgrp { fsl,pins =3D < MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0 --=20 2.25.1 From nobody Tue Apr 7 10:40:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7985ECAAD2 for ; Mon, 29 Aug 2022 08:33:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229564AbiH2Id3 (ORCPT ); Mon, 29 Aug 2022 04:33:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36190 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229981AbiH2IdI (ORCPT ); Mon, 29 Aug 2022 04:33:08 -0400 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D63A857E20; Mon, 29 Aug 2022 01:33:04 -0700 (PDT) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 7E0491A2CA6; Mon, 29 Aug 2022 10:33:02 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id C32821A2CC0; Mon, 29 Aug 2022 10:33:01 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id C5A0E1820F59; Mon, 29 Aug 2022 16:32:59 +0800 (+08) From: Richard Zhu To: p.zabel@pengutronix.de, l.stach@pengutronix.de, bhelgaas@google.com, lorenzo.pieralisi@arm.com, robh@kernel.org, shawnguo@kernel.org, vkoul@kernel.org, alexander.stein@ew.tq-group.com, marex@denx.de, richard.leitner@linux.dev Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com, Richard Zhu Subject: [PATCH v4 6/6] PCI: imx6: Add iMX8MP PCIe support Date: Mon, 29 Aug 2022 16:15:17 +0800 Message-Id: <1661760917-9558-7-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1661760917-9558-1-git-send-email-hongxing.zhu@nxp.com> References: <1661760917-9558-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add i.MX8MP PCIe support. Signed-off-by: Richard Zhu Tested-by: Marek Vasut Tested-by: Richard Leitner Tested-by: Alexander Stein --- drivers/pci/controller/dwc/pci-imx6.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index 6e5debdbc55b..786f5737ca6a 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -51,6 +51,7 @@ enum imx6_pcie_variants { IMX7D, IMX8MQ, IMX8MM, + IMX8MP, }; =20 #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) @@ -150,7 +151,8 @@ struct imx6_pcie { static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie) { WARN_ON(imx6_pcie->drvdata->variant !=3D IMX8MQ && - imx6_pcie->drvdata->variant !=3D IMX8MM); + imx6_pcie->drvdata->variant !=3D IMX8MM && + imx6_pcie->drvdata->variant !=3D IMX8MP); return imx6_pcie->controller_id =3D=3D 1 ? IOMUXC_GPR16 : IOMUXC_GPR14; } =20 @@ -301,6 +303,7 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_p= cie) { switch (imx6_pcie->drvdata->variant) { case IMX8MM: + case IMX8MP: /* * The PHY initialization had been done in the PHY * driver, break here directly. @@ -558,6 +561,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *i= mx6_pcie) break; case IMX8MM: case IMX8MQ: + case IMX8MP: ret =3D clk_prepare_enable(imx6_pcie->pcie_aux); if (ret) { dev_err(dev, "unable to enable pcie_aux clock\n"); @@ -602,6 +606,7 @@ static void imx6_pcie_disable_ref_clk(struct imx6_pcie = *imx6_pcie) break; case IMX8MM: case IMX8MQ: + case IMX8MP: clk_disable_unprepare(imx6_pcie->pcie_aux); break; default: @@ -669,6 +674,7 @@ static void imx6_pcie_assert_core_reset(struct imx6_pci= e *imx6_pcie) reset_control_assert(imx6_pcie->pciephy_reset); fallthrough; case IMX8MM: + case IMX8MP: reset_control_assert(imx6_pcie->apps_reset); break; case IMX6SX: @@ -744,6 +750,7 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pc= ie *imx6_pcie) break; case IMX6Q: /* Nothing to do */ case IMX8MM: + case IMX8MP: break; } =20 @@ -793,6 +800,7 @@ static void imx6_pcie_ltssm_enable(struct device *dev) case IMX7D: case IMX8MQ: case IMX8MM: + case IMX8MP: reset_control_deassert(imx6_pcie->apps_reset); break; } @@ -812,6 +820,7 @@ static void imx6_pcie_ltssm_disable(struct device *dev) case IMX7D: case IMX8MQ: case IMX8MM: + case IMX8MP: reset_control_assert(imx6_pcie->apps_reset); break; } @@ -1179,6 +1188,7 @@ static int imx6_pcie_probe(struct platform_device *pd= ev) } break; case IMX8MM: + case IMX8MP: imx6_pcie->pcie_aux =3D devm_clk_get(dev, "pcie_aux"); if (IS_ERR(imx6_pcie->pcie_aux)) return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux), @@ -1320,6 +1330,10 @@ static const struct imx6_pcie_drvdata drvdata[] =3D { .variant =3D IMX8MM, .flags =3D IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, }, + [IMX8MP] =3D { + .variant =3D IMX8MP, + .flags =3D IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, + }, }; =20 static const struct of_device_id imx6_pcie_of_match[] =3D { @@ -1329,6 +1343,7 @@ static const struct of_device_id imx6_pcie_of_match[]= =3D { { .compatible =3D "fsl,imx7d-pcie", .data =3D &drvdata[IMX7D], }, { .compatible =3D "fsl,imx8mq-pcie", .data =3D &drvdata[IMX8MQ], }, { .compatible =3D "fsl,imx8mm-pcie", .data =3D &drvdata[IMX8MM], }, + { .compatible =3D "fsl,imx8mp-pcie", .data =3D &drvdata[IMX8MP], }, {}, }; =20 --=20 2.25.1